Design of a logic synthesis system (tutorial)

Rudell, R.

doi:10.1145/240518.240554

Cited by 7 publications

(1 citation statement)

References 13 publications

(7 reference statements)

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“…Because each edge will be visited once at most, the cost for the worst case is proportional to the number of edges. Cube extraction (Rudell, 1996) was applied to a diagram here to reduce edges, as well as other optimizations. Details are discussed in Kaneko et al (2001).…”

Section: Incremental Matching With a Diagrammentioning

confidence: 99%

Automated Identification of Patterns in Evaluation Functions

Kaneko

Yamaguchi

Kawai

2004

Advances in Computer Games

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This pa per proposes a general and automated method that generates accurate evaluation functions, without expert players' knowledge of a target game. Patterns (which are partial descriptions of a game state) are widely used as primitives of evaluation functions in game programming. They ha veto be carefully selected in order to generate accurate evaluation functions. Our approach consists of three steps: (1) generation of logic formulae by using the specifications of a target game, (2) translation of the formulae into patterns, and (3) selection of a set of suitable patterns from those generated. The problem, in the automated identification of suitable patterns, is that it is difficult either to generate only useful patterns or to examine ali possible patterns. The latter obstacle is due to the prohibi ti ve numbers involved. We solved this dilemma by a combination of two methods, where one method generates patterns of good quality, and the other method entails a lightweight selection based on statistics that could handle a large number of candidates. Experiments in Othello revealed that about 100,000 patterns from more than eight million automatically generated patterns could be successfully selected with our method, and that accurate evaluation functions were constructed. This accuracy is comparable to that of specialized Othello programs and is much better than that of the evaluation functions generated by existing general methods.

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Section: Incremental Matching With a Diagrammentioning

confidence: 99%

Automated Identification of Patterns in Evaluation Functions

Kaneko

Yamaguchi

Kawai

2004

Advances in Computer Games

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Behavioral network graph unifying the domains of high-level and logic synthesis

Bergamaschi¹

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

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High-level synthesis operates on internal models known as control data ow graphs CDFG and produces a registertransfer-level RTL model of the hardware implementation for a given schedule. For high-level synthesis to be e cient it has to estimate the e ect that a given algorithmic decision e.g., scheduling, allocation will have on the nal hardware implementation after logic synthesis. Currently, this e ect cannot be measured accurately because the CDFGs are very distinct from the RTL gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.

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Technology mapping for minimizing gate and routing area

Lu¹,

Stenz²,

Johannes³

Proceedings Design, Automation and Test in Europe

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This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.

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Design of a logic synthesis system (tutorial)

Cited by 7 publications

References 13 publications

Automated Identification of Patterns in Evaluation Functions

Automated Identification of Patterns in Evaluation Functions

Behavioral network graph unifying the domains of high-level and logic synthesis

Technology mapping for minimizing gate and routing area

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