Technology mapping for minimizing gate and routing area

Abstract

This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

“…The first heuristic, called area flow, is closely related to the area of a mapping solution and can be optimized using a dynamic programming formulation. Area flow is similar to the area measurement techniques presented in [10] (applicable to MFFCs) and [20] (applicable to standard cell mapping). The second heuristic determines a depth bound that must be met by each LUT used to cover the initial circuit in order to meet some depth requirement in the mapped circuit.…”