In this paper, we present a new approach that performs timing driven placement for standard cell circuits in interaction with netlist transformations.As netlist transformations are integrated into the placement process, an accurate net delay model is available. This model provides the basis for effective netlist transformations.In contrast to previous approaches that apply netlist transformations during placement, we are not restricted to local transformations like fanout buffering or gate resizing. Instead, we exploit global dependencies between the signals in the circuit. Results for benchmark circuits show excellent placement quality. The maximum path delay is reduced up to 33 % compared to the initial timing driven placement of the original netlist and up to 18 % compared to the results obtained by consecutive optimization of the netlist and timing driven placement of the optimized netlist. This delay reduction is achieved with almost no increase in chip area.
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This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.
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