Timing driven placement in interaction with netlist transformations

Stenz, G.; Riess, B.M.; Rohfleisch, Bernhard; Johannes, Frank

doi:10.1145/267665.267676

Cited by 39 publications

(17 citation statements)

References 11 publications

(9 reference statements)

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“…This need for fewer exceptional wires is the core reason that researchers are exploring new methodologies that use variable width routing, metal promotion, synthesis-driven layout techniques [16], layout-driven synthesis techniques [3], postlayout resynthesis optimizations [17] [18], and combining layout and synthesis [19].…”

Section: Cad Implicationsmentioning

confidence: 99%

Interconnect Scaling Implications for CAD

Ho¹,

Mai²,

Kapadia³

et al. 1999

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Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention. IntroductionWith process technologies capable of fabricating a billion transistor chip on the horizon, the CAD community faces many new challenges. Notably, interconnect scaling in deep submicron processes may force a fundamental change in current ASIC design methodologies. If interconnect delay becomes a significant fraction of total delay, timing convergence for standard-cell design blocks will become difficult or impossible to achieve with current, crude, fanout-based wire load models. Designers will need new tools and methods to synthesize large blocks in deep submicron technologies.In a 1998 ICCAD tutorial, Sylvester and Keutzer carried out a detailed analysis of interconnect scaling and its potential effects on CAD methodologies [1] [2]. By examining the scaling of average length wires, they concluded that CAD tools are adequate for future module-level designs. We examine the sensitivity of their analysis to a range of possible technology scaling assumptions by modeling their simulations with an RC tree delay model.Since design speeds and timing convergence in synthesis flows are typically constrained by long wires, not averagelength ones, we extend the analysis to long wires. We show that for a fixed complexity design, the number of long wires grows slowly with scaling. If chip complexity remained constant, this increase in long wires could be handled by small improvements in today's CAD design flow. Unfortunately exponentially increasing die capacity exacerbates the increasing number of long wires per module by driving up the number of modules. Thus, with constant design team size, the number of gates per designer will grow exponentially. To prevent the per-designer workload from also growing exponentially the percentage of wires that need manual intervention must fall exponentially. This implies that future tools must handle a greater per...

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Section: Cad Implicationsmentioning

confidence: 99%

Interconnect Scaling Implications for CAD

Ho¹,

Mai²,

Kapadia³

et al. 1999

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“…In [8,11,28], post-placement resynthesis achieved delay improvement with limited placement perturbation, but these techniques are limited to simple signal substitution transformations. As the major portion of the critical delay is shifting into interconnect [32], poor design choices during synthesis cannot be easily corrected by limited scale post-placement optimizations.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

Plaza

Markov

Bertacco

2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the specified performance objectives. Such iterations are often due to the difficulty of early delay estimation, especially before placement. Therefore, effective logic restructuring to reduce interconnect delay has been a major challenge in physical synthesis, a phase during which more accurate delay estimates can be finally gathered. In this work, we develop a new approach to this problem that enhances modern highperformance logic synthesis techniques with flexibility and accuracy in the physical domain. This approach is based on (1) a novel criterion based on path monotonicity, that identifies those interconnects amenable to optimization through logic restructuring and (2) a synthesis algorithm relying on logic simulation and placement information to identify placed subcircuits that hold promise for interconnect reduction. Experiments indicate that our techniques find optimization opportunities and improve interconnect delay by 11.7% on average at less than 2% wirelength and area overhead.

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“…Liu et al [11] presented a resynthesis technique that resynthesizes the most congested region of the chip to reduce routing area. Stenz et al [12] proposed a timing-driven placement method in interaction with netlist transformations. The netlist transformation procedure is integrated into the placement process so that accurate delay models are available to guide the transformation process.…”

Section: Introductionmentioning

confidence: 99%

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

Lin

1999

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delays on an average of 22%. Furthermore, the results show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in chip area.

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Timing driven placement in interaction with netlist transformations

Cited by 39 publications

References 11 publications

Interconnect Scaling Implications for CAD

Interconnect Scaling Implications for CAD

Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring

A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning

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