Interconnect Scaling Implications for CAD

Abstract

Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by Sylvester and Keutzer examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. In our work, we show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design, will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention. IntroductionWith process technologies capable of fabricating a billion transistor chip on the horizon, the CAD community faces many new challenges. Notably, interconnect scaling in deep submicron processes may force a fundamental change in current ASIC design methodologies. If interconnect delay becomes a significant fraction of total delay, timing convergence for standard-cell design blocks will become difficult or impossible to achieve with current, crude, fanout-based wire load models. Designers will need new tools and methods to synthesize large blocks in deep submicron technologies.In a 1998 ICCAD tutorial, Sylvester and Keutzer carried out a detailed analysis of interconnect scaling and its potential effects on CAD methodologies [1] [2]. By examining the scaling of average length wires, they concluded that CAD tools are adequate for future module-level designs. We examine the sensitivity of their analysis to a range of possible technology scaling assumptions by modeling their simulations with an RC tree delay model.Since design speeds and timing convergence in synthesis flows are typically constrained by long wires, not averagelength ones, we extend the analysis to long wires. We show that for a fixed complexity design, the number of long wires grows slowly with scaling. If chip complexity remained constant, this increase in long wires could be handled by small improvements in today's CAD design flow. Unfortunately exponentially increasing die capacity exacerbates the increasing number of long wires per module by driving up the number of modules. Thus, with constant design team size, the number of gates per designer will grow exponentially. To prevent the per-designer workload from also growing exponentially the percentage of wires that need manual intervention must fall exponentially. This implies that future tools must handle a greater per...

Performance analysis and optimization of latency insensitive systems

“…In this perspective, it is necessary to define a methodology which effectively addresses the increasing impact of interconnect delay in future design generations. Despite the increase in number of layers and in aspect ratio, the RC delay of an average metal line with constant length is getting worse with each process generation [18,22]. This effect, combined with the increases in operating frequency, die size, and average interconnect length, makes interconnect delay becoming a larger fraction of the clock cycle time [19].…”

Limits on fundamental limits to computation

“…Completing new IC designs, optimizing and verifying them requires great effort and continuing innovation, e.g., the lack of scalable design automation is a limiting factor for analog ICs [30,31]. In 1999, bottom-up analysis of digital IC technologies [15,32] outlined design scaling up to selfcontained modules with 50K standard cells (each cell contains 1-3 logic gates), but further scaling was limited by global interconnect. In 2010, physical separation of modules became less critical, as large-scale placement optimizations assumed greater responsibility for IC layout and learned to blend nearby modules [33,34].…”

High-performance interconnects: an integration overview

“…These changes, while extremely challenging, are to a certain extent evolutionary since traditional wiring technology will be employed. However, recent simulations [19] predict that in spite of these material changes the performance roadmap will not be met. Revolutionary approaches are needed to meet the performance challenge, and several new candidate interconnect technologies will be discussed in Section III.…”