High-performance interconnects: an integration overview

Havemann, R.H.; Hutchby, J.A.

doi:10.1109/5.929646

Cited by 282 publications

(134 citation statements)

References 29 publications

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“…It is, instead, the interface between the two dissimilar metals that dominates the total resistance. At present, tungsten is used as a chip-level interconnect in complementary metal-oxide-semiconductor (CMOS) circuits (5,29) in contact with copper, an FCC metal where conductance is dominated by slike modes (30). These findings suggest that, as semiconductor devices shrink farther to ballistic scales, counterintuitive interface effects are liable to dominate device resistance, particularly for metals with dissimilar electronic structure.…”

Section: Discussionmentioning

confidence: 99%

Conductivity of an atomically defined metallic interface

Oliver

Maassen

Ouali

et al. 2012

Proc. Natl. Acad. Sci. U.S.A.

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A mechanically formed electrical nanocontact between gold and tungsten is a prototypical junction between metals with dissimilar electronic structure. Through atomically characterized nanoindentation experiments and first-principles quantum transport calculations, we find that the ballistic conduction across this intermetallic interface is drastically reduced because of the fundamental mismatch between s wave-like modes of electron conduction in the gold and d wave-like modes in the tungsten. The mechanical formation of the junction introduces defects and disorder, which act as an additional source of conduction losses and increase junction resistance by up to an order of magnitude. These findings apply to nanoelectronics and semiconductor device design. The technique that we use is very broadly applicable to molecular electronics, nanoscale contact mechanics, and scanning tunneling microscopy.atomic force microscopy | surface science

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Section: Discussionmentioning

confidence: 99%

Conductivity of an atomically defined metallic interface

Oliver

Maassen

Ouali

et al. 2012

Proc. Natl. Acad. Sci. U.S.A.

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“…The performance of ICs in advanced technology nodes is dominated by the interconnect delay [Havemann and Hutchby 2001]. Migrating to 3D ICs, we can envisage reduced interconnect delay and chip area which is achieved by placing the logic gates, on the critical path, very close to each other using multiple active layers.…”

Section: Introductionmentioning

confidence: 99%

Cell transformations and physical design techniques for 3D monolithic integrated circuits

Bobba

Chakraborty

Thomas

et al. 2013

J. Emerg. Technol. Comput. Syst.

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3D Monolithic Integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. In 3DMI technology the 3D contacts, connecting different active layers, are in the order of few 100nm. Given the advantage of such small contacts, 3DMI enables fine-grain (gate-level) partitioning of circuits. In this work we present three cell transformation techniques for standard cell-based ICs with 3DMI technology. As a major contribution of this work, we propose a design flow comprising of a cell transformation technique, cell-on-cell stacking, and a physical design technique (CELONCEL PD ) aimed at placing cells transformed with cell-on-cell stacking. We analyze and compare various cell transformation techniques for 3DMI technology without disrupting the regularity of the IC design flow. Our experiments demonstrate the effectiveness of CELONCEL design technique, yielding us an area reduction of 37.5%, 16.2% average reduction in wirelength, and 6.2% average improvement in overall delay, compared with a 2D case when benchmarked across various designs in 45nm technology node.

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“…1 A major obstacle preventing this growth from continuing is the limited onboard bandwidth provided by electrical interconnects. 2 The move to low loss copper lines from aluminium and the development of superior interconnect protocols has stretched the lifetime of the these interconnects. 3 However, a long term solution is needed to allow for the bandwidth which will be required in the future.…”

Section: Introductionmentioning

confidence: 99%

Derivation and examination of a comprehensive free-space optical interconnect link equation

2004

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Free-space optical interconnects (FSOIs) utilize arrays of vertical-cavity surface emitting lasers (VCSELs), microlenses, and photodetectors to effectively overcome the communication bottleneck caused by the poor performance of electrical interconnects. We derived a comprehensive FSOI link equation which can be used to determine the interconnect performance parameters, such as the receiver carrier-to-noise ratio. The link equation includes both optical and electrical noise components. The optical noise component is caused mainly by laser beam diffraction. We have simplified the modelling of optical noise by using the recently introduced Mode Expansion Method. The optical noise component strongly depends on the modal content of the incident VCSEL beam. The models used in the literature assume that the cross-sectional profile of the emitted laser beam resembles the fundamental Gaussian mode. Our link equation takes into account the modal structure of a multimode VCSEL beam. We have investigated the FSOI performance and we found that for each merit function there exists a single set of design parameters yielding the optimal performance. We have also found that the presence of higher-order modes negatively affects the performance. Our results show that FSOIs based on multimode VCSELs can be utilized in chip-level interconnects despite increased beam diffraction.

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High-performance interconnects: an integration overview

Cited by 282 publications

References 29 publications

Conductivity of an atomically defined metallic interface

Conductivity of an atomically defined metallic interface

Cell transformations and physical design techniques for 3D monolithic integrated circuits

Derivation and examination of a comprehensive free-space optical interconnect link equation

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