High-level synthesis operates on internal models known as control data ow graphs CDFG and produces a registertransfer-level RTL model of the hardware implementation for a given schedule. For high-level synthesis to be e cient it has to estimate the e ect that a given algorithmic decision e.g., scheduling, allocation will have on the nal hardware implementation after logic synthesis. Currently, this e ect cannot be measured accurately because the CDFGs are very distinct from the RTL gate-level models used by logic synthesis, precluding interaction between high-level and logic synthesis. This paper presents a solution to this problem consisting of a novel internal model for synthesis which spans the domains of high-level and logic synthesis. This model is an RTL gate-level network capable of representing all possible schedules that a given behavior may assume. This representation allows high-level synthesis algorithms to be formulated as logic transformations and effectively interleaved with logic synthesis.
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