Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling

Hattori,; Nakashima,; Kuwahara,; Yoshida, Minoru; Yamauchi,; Yamaguchi, Naohito

doi:10.1109/wct.2004.239903

Cited by 21 publications

(10 citation statements)

References 4 publications

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“…The BV and FOM of Figure 10. R SP as a function of the BV for the one-dimensional silicon limit, two-dimensional charge-coupling limits for the pitches of 4 and 8 µm, references [10,26,27], and this work.…”

Section: Resultsmentioning

confidence: 90%

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

et al. 2019

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In this study, a split-gate resurf stepped oxide with a floating electrode (FSGRSO) UMOSFET has been proposed. The source in the trench is divided into two electrodes, namely: the upper electrode and the lower electrode. The upper one is the floating electrode, which redistributes the electric potential vertically, and improves the breakdown voltage and figure of merit (FOM). The breakdown (BV) and FOM of the FSGRSO UMOSFET have been improved up to 27.3% and 62.7%, respectively, compared with the SGRSO UMOSFET, according to the simulation results.

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Section: Resultsmentioning

confidence: 90%

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

et al. 2019

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“…The superjunction pillars can run in the third dimension parallel to the trench width or perpendicular to it. 50 The latter has the advantage that no precise alignment is needed between the superjunction structures and the gated channels. Such design is more appropriate for very narrow superjunction pillars.…”

Section: Superjunctionmentioning

confidence: 99%

Multidimensional device architectures for efficient power electronics

2022

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Power semiconductor devices are key to delivering high efficiency energy conversion in power electronics systems, which is critical towards efforts in reducing energy loss, cutting carbon dioxide emissions and creating more sustainable technology. While the use of wide or ultra-wide bandgap materials will be required in order to create improved power devices, multidimensional architectures can also improve performance, regardless of the underlying material technology. In particular, multidimensional device architectures -such as superjunction, multi-channel and multi-gate technologies -can enable advances in the speed, efficiency, and form factor of power electronics systems. Here we review the development of multidimensional device architectures for efficient power electronics. We explore the rationale for using multidimensional architectures and the different architectures available. We also consider the performance limits, scaling, and material figure-of-merits of the architectures, and identify key technological challenges that need to be addressed in order to realize the full potential of the approach.

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“…The parameters that were used for the single-EPI, double-EPIs, and triple-EPIs structure simulation. Figure 12 compares the specific on-resistance performance of our proposed SGT devices with that of the other middle-voltage devices reported in [4,15,21,[32][33][34][35][36][37][38][39][40], ideal silicon limit, and super junction (SJ) limit for cell pitch = 5 and 10 µm in the 50-200 V range. Form Figure 12, we observe that the triple-EPIs structure and those using a double split-gate device [15] and stepped oxide SGTs [18,20,21] can achieve a very low R on,sp in the middle-voltage range because they all can maintain more uniform EF distributions between two trenches.…”

Section: Devicementioning

confidence: 99%

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

et al. 2020

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A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

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Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling

Abstract: A new super junction trench MOSFET which has n-huffer regions hetween trench gates and n columns was designed and demonstrated. In this structure, the speeiSc nn-resistance (RON) does not increase as long as the trench gate

Cited by 21 publications

References 4 publications

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

Simulation and Result Analysis of Split Gate Resurf Stepped Oxide UMOFSET with Floating Electrode for Improved Performance

Multidimensional device architectures for efficient power electronics

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

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