Neural networks based on memristive devices [1][2][3] have shown potential in substantially improving throughput and energy efficiency for machine learning [4] and artificial intelligence [5], especially in edge applications. [6][7][8][9][10][11][12][13][14][15][16][17][18][19] Because training a neural network model from scratch is very costly, it is impractical to do it individually on billions of memristive neural networks distributed at the edge. A practical approach would be to download the synaptic weights obtained from the cloud training and program them directly into memristors for the commercialization of edge applications (Figure 1a). Some posttuning in memristor conductance to adapt local situations may follow afterward or during applications. Therefore, a critical requirement on memristors for neural network applications is a high-precision programming ability to guarantee uniform and accurate performance across a massive number of memristive networks. [20][21][22][23][24][25][26] That translates into the requirement of many distinguishable conductance levels on each memristive device, not just lab-made devices but more importantly, devices fabricated in foundries. High precision memristors also benefit other neural network applications, such as training and scientific computing. [23,27] Here we report over 2048 conductance levels, the largest number among all types of memories ever reported, achieved with memristors in fully integrated chips with 256 ´ 256 memristor arrays monolithically integrated on CMOS circuits in a standard foundry. We have unearthed the underlying physics that previously limited the number of achievable conductance levels in memristors and developed electrical operation protocols to circumvent such limitations. These results reveal insights into the fundamental understanding of the microscopic picture of memristive switching and provide approaches to enable high-precision memristors for various applications.Memristive switching devices are known for their relatively large dynamical range of conductance, which can potentially lead to a large number of discrete conductance levels. However, the highest number reported to date has been no more than two hundred. [20]

Power semiconductor devices are key to delivering high efficiency energy conversion in power electronics systems, which is critical towards efforts in reducing energy loss, cutting carbon dioxide emissions and creating more sustainable technology. While the use of wide or ultra-wide bandgap materials will be required in order to create improved power devices, multidimensional architectures can also improve performance, regardless of the underlying material technology. In particular, multidimensional device architectures -such as superjunction, multi-channel and multi-gate technologies -can enable advances in the speed, efficiency, and form factor of power electronics systems. Here we review the development of multidimensional device architectures for efficient power electronics. We explore the rationale for using multidimensional architectures and the different architectures available. We also consider the performance limits, scaling, and material figure-of-merits of the architectures, and identify key technological challenges that need to be addressed in order to realize the full potential of the approach.

random-access memory (DRAMs), static random-access memory (SRAMs), [1] and flash memory, [2] multiple transistors and capacitors are employed to constitute a single functional cell. These functional cells are typically integrated to form a memory array for advanced functionality, miniaturized footprints, low power consumption, and reduced latency. Traditional silicon-based complementary metal-oxidesemiconductor (CMOS) technology has been widely used to build these memory arrays. However, the performance improvement of CMOS-based memory relies on the advance of nanofabrication technology to scale down the feature size of transistors, which is approaching the physical limit. [3] To overcome this bottleneck, emerging memory technologies are brought up as promising supplements to conventional memory devices. [4] These novel types of memory include resistive random-access memory (RRAM), [5,6] ferroelectric RAM (FeRAM), [7] optoelectronic RRAM (ORRAM), [8,9] phase-change memory (PCM), [10] and spin-transfer torque magnetoresistive RAM (STT-MRAM). [11,12] Furthermore, emerging memory devices allow non-von-Neumann architectures that pave the way toward high-performance in-memory computing technology. [13,14] For example, memristive crossbar arrays composed of 1-transistor-1-resistor (1T1R) unit cells can enable in-memory computing and are the most cost-efficient thanks to their two-terminal structure. [15] Advanced 3D monolithic stacking integration also emerges as a promising approach to Memory technologies and applications implemented fully or partially using emerging 2D materials have attracted increasing interest in the research community in recent years. Their unique characteristics provide new possibilities for highly integrated circuits with superior performances and low power consumption, as well as special functionalities. Here, an overview of progress in 2D-material-based memory technologies and applications on the circuit level is presented. In the material growth and fabrication aspects, the advantages and disadvantages of various methods for producing large-scale 2D memory devices are discussed. Reports on 2D-material-based integrated memory circuits, from conventional dynamic random-access memory, static random-access memory, and flash memory arrays, to emerging memristive crossbar structures, all the way to 3D monolithic stacking architecture, are systematically reviewed. Comparisons between experimental implementations and theoretical estimations for different integration architectures are given in terms of the critical parameters in 2D memory devices. Attempts to use 2D memory arrays for in-memory computing applications, mostly on logic-in-memory and neuromorphic computing, are summarized here. Finally, challenges that impede the large-scale applications of 2D-material-based memory are reviewed, and perspectives on possible approaches toward a more reliable system-level fabrication are also given, hopefully shedding some light on future research.

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In high-performance flexible and stretchable electronic devices, conventional inorganic semiconductors made of rigid and brittle materials typically need to be configured into geometrically deformable formats and integrated with elastomeric substrates, which leads to challenges in scaling down device dimensions and complexities in device fabrication and integration. Here we report the extraordinary mechanical properties of the newly discovered inorganic double helical semiconductor tin indium phosphate. This spiral-shape double helical crystal shows the lowest Young’s modulus (13.6 GPa) among all known stable inorganic materials. The large elastic (>27%) and plastic (>60%) bending strains are also observed and attributed to the easy slippage between neighboring double helices that are coupled through van der Waals interactions, leading to the high flexibility and deformability among known semiconducting materials. The results advance the fundamental understanding of the unique polymer-like mechanical properties and lay the foundation for their potential applications in flexible electronics and nanomechanics disciplines.