Design methods of multithreaded architectures for multicore microcontrollers

Caprita, Horia V.; Popa, M.

doi:10.1109/saci.2011.5873041

Cited by 5 publications

(2 citation statements)

References 10 publications

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“…Defining the optimal number of pipeline stages from the number of instructions per cycle (IPC) given in [28] is not possible, as the three cores are based on different ISA subsets. A more homogeneous set of cores is Klessydra [34], a VHDL (VHSIC hardware description language) model of a RISC-V processor (RV32IM) designed for the PULPino SoC with a configurable pipeline of 2, 3, and 4 stages and supporting up to 4 hardware threads with a simple fine-grained implementation that changes thread every clock cycle (independently from whether the current one is stalled or not) [35].…”

Section: A Microcontrollersmentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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This paper proposes a roadmap to address present and future needs in space systems with RISC-V processors. RISC-V is an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based on RISC-V are proposed for each of these types of processors and compared with proprietary commercial-off-the-shelf and spacegrade solutions. An extensive analysis of the results available from literature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systems could benefit from many of those developments, and this work identifies and highlights what is still missing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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Section: A Microcontrollersmentioning

confidence: 99%

Leveraging the Openness and Modularity of RISC-V in Space

Mascio¹,

Menicucci²,

Gill³

et al. 2019

Journal of Aerospace Information Systems

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show abstract

“…The experimental results mentioned in table 5 and table 6 explain how function execution time varies with architecture which is illustrated in figure 10. Not only the architecture but also the number of threads [32] is important the execution time of a machine. In parallelcomputation all the CPUs are treated as individual entity which are connected to each other for better communication and it executes all the threads at the same time, which could be proven with the help of figure 11, it could also be observed with the same diagram that every function has a different time boundation that is also known as time bounded computation.The execution speed of Intel ® i3 to Intel ® [33] i5 reduces as the frequency of the device increases its results are illustrated in table 6.Aftercomparing the results mentioned in tables 5 and 9 the conclusion is that the good amount of possibility that multicore arc.…”

Section: Time Critical Analysis Of Sequential and Parallel Tasks On Mmentioning

confidence: 99%

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Saini¹,

Bansal²,

Sharma³

2015

IJESA

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1.INTRODUCTIONIn the present era of technology, computational power [1] plays an important role. The multicore microprocessor devices [2] are already available in CISC architecture which used to perform non real time computing. Recently there has been a huge demand of high computing speed in time critical system, mostly in real time embedded device. Technology is growing exponentially every day with the demand of more power and processing handling capabilities. The basic need of a multicore system is the distributed and parallel computing [3]. Time consumption is the drawback of single core processors, so multicore [4] technology is used to achieve efficiency through parallel processing. Parallel processing [5] is the simultaneous use of more than one CPU to execute a program or multiple computational threads. The main goal of parallel processing is a high performance [6] computing, which speedup the execution time of the program. Parallel [7] processing makes programs run faster because there are more engines (CPUs or cores) workingon it. It increases the efficiency, safe execution time, take less energy and retain the time. Multicore has two or more CPUs while the single core has only one core inside it as illustrated in figure1. To enhance the performance [8] of single core processor, it is mandatory to increase the frequency as CPU load increases. It causes heat losses and leakage current so rather than increase the clock frequency of single core, manufacture switched to multicore to avoid the power [9] consumption problem and to increase speed and efficiency.

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Multithreaded Peripheral Processor for a Multicore Embedded System

Caprita

Popa

2012

Applied Computational Intelligence in Engineering and Information Technology

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Design methods of multithreaded architectures for multicore microcontrollers

Cited by 5 publications

References 10 publications

Leveraging the Openness and Modularity of RISC-V in Space

Leveraging the Openness and Modularity of RISC-V in Space

Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Multithreaded Peripheral Processor for a Multicore Embedded System

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