Time Critical Multitasking For Multicore Microcontroller Using Xmos® Kit

Abstract

1.INTRODUCTIONIn the present era of technology, computational power [1] plays an important role. The multicore microprocessor devices [2] are already available in CISC architecture which used to perform non real time computing. Recently there has been a huge demand of high computing speed in time critical system, mostly in real time embedded device. Technology is growing exponentially every day with the demand of more power and processing handling capabilities. The basic need of a multicore system is the distributed and parallel computing [3]. Time consumption is the drawback of single core processors, so multicore [4] technology is used to achieve efficiency through parallel processing. Parallel processing [5] is the simultaneous use of more than one CPU to execute a program or multiple computational threads. The main goal of parallel processing is a high performance [6] computing, which speedup the execution time of the program. Parallel [7] processing makes programs run faster because there are more engines (CPUs or cores) workingon it. It increases the efficiency, safe execution time, take less energy and retain the time. Multicore has two or more CPUs while the single core has only one core inside it as illustrated in figure1. To enhance the performance [8] of single core processor, it is mandatory to increase the frequency as CPU load increases. It causes heat losses and leakage current so rather than increase the clock frequency of single core, manufacture switched to multicore to avoid the power [9] consumption problem and to increase speed and efficiency.

Development of typical "state" software patterns for Cortex­M microcontrollers in real time

“…It stores the current value of the ASC state. Thus, below is the classical software implementation of mathematical model (3). It is implemented in the procedural variant.…”

“…In the header file, we use the enumerator enum Z_State to describe the set of states, forming the finite set of the internal ASC states, which corresponds to (3). If necessary, a developer can increase this number to the required value.…”

“…A given formula provides an opportunity to implement a mathematical model in the form of a State software pattern for ASC in a procedural paradigm in the classic version of the Polled Loop Systems or based on the microcontroller Interrupt Driven system according to the classification given in [1,2]. Next, we show the result of the development of a header file for the software, which demonstrates the presence of all three sets in formula (3). A given file demonstrates exclusively the idea of the developed State software pattern in the procedural paradigm, in the variant of Polled Loop Systems in accordance with the classification of RTOS given in [1,2].…”

“…Paper [3] explores the possibility of increasing the speed of the software by increasing the number of MC computational cores. At the same time, the task of increasing the speed of performance at minimal cost remains unresolved.…”

“…One of the solutions to the above issues concerning the hardware of the ASC prototype, outlined in [3][4][5][6][7][8] is the use of relatively inexpensive general-purpose Cortex-M architecture MCs.…”