Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS

Miyake, Takao; Yamashita, T.; Asari, N.; Sekisaka, H.; Sakai, Takeyasu; Matsuura, Kai; Wakahara, A.; Takahashi, H.; Hiyama, T.; Miyamoto, Koji; Mori, K.

doi:10.1109/cicc.2001.929773

Cited by 14 publications

(15 citation statements)

References 1 publication

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“…In addition to these commercial accomplishments, chip demonstrators with V DD and V th scaling capabilities have also been reported in the literature archival [4]- [8]. Other reported uses of V DD and V th scaling, besides power management in processors, are in testing [9], product binning [10], and yield tuning [11].…”

Section: Introductionmentioning

confidence: 99%

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Meijer

Pessolano

Gyvez

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modern deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8x power savings by 3.4x frequency downscaling using AVS, ±11% power and ±8% frequency tuning at nominal conditions using ABB only, 22x power savings with 5x frequency downscaling by combining AVS and ABB, as well as 22x leakage reduction.

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Section: Introductionmentioning

confidence: 99%

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Meijer

Pessolano

Gyvez

2004

Proceedings of the 2004 International Symposium on Low Power Electronics and Design

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show abstract

“…In addition to these commercial accomplishments, chip demonstrators with V DD and V th scaling capabilities have also been reported in the literature archival [6][7][8]. Other reported uses of V DD and V th scaling, besides power management in processors, are in testing [9], product binning [10], and yield tuning [11].…”

Section: Adaptive Power Performance Tuning Of Icsmentioning

confidence: 96%

Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning

Meijer

Gyvez

2008

Adaptive Techniques for Dynamic Processor Optimization

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“…Specifically, we discuss methods for taking advantage of the ability to control semiconductor body biases (wells and substrates) independently from the chip VDD and GND. Taking advantage of that control has been suggested for IDDQ test [3,11,12], as "good chip" background leakage can be decreased during IDDQ test to increase sensitivity to elevated defect-related currents.…”

Section: Introductionmentioning

confidence: 97%

“…Such methods have been applied for microprocessors and other circuit types [1][2][3][4][5][6][7][8][9]. Given the exponential dependence of subthreshold leakage current on Vt, such a method is very effective for decreasing chip power during low-load or idle states.…”

Section: Introductionmentioning

confidence: 99%

Using well/substrate bias manipulation to enhance voltage-test-based defect detection

Gattiker

Nigh²

2011

2011 IEEE International Test Conference

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This paper proposes methods for taking advantage during voltage-based production test of the capability to control well and substrate (body) biases separately from the chip's VDD and GND. Such control is a by-product of a low-power design strategy that allows parts or all of the chip to go into low-power reduced-leakage states. The proposed test methods use body bias manipulation to increase or decrease transistor threshold voltages. Unlike related methods that rely on weakening transistors, the proposed methods are shown to enhance defect detectability by both weakening and strengthening transistors and by exploiting the ability to weaken/strengthen nfets/pfets separately.

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Design methodology of high performance microprocessor using ultra-low threshold voltage CMOS

Cited by 14 publications

References 1 publication

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning

Using well/substrate bias manipulation to enhance voltage-test-based defect detection

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