In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modern deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8x power savings by 3.4x frequency downscaling using AVS, ±11% power and ±8% frequency tuning at nominal conditions using ABB only, 22x power savings with 5x frequency downscaling by combining AVS and ABB, as well as 22x leakage reduction.

Abstract-In this paper we examine technology constraints on tuning active power and delay using adaptive voltage scaling (AVS) and adaptive body biasing (ABB) design techniques. To serve this purpose, a test circuit was fabricated in a 90nm triple-well low-power CMOS technology. The analysis hereby presented is based on a ring oscillator running at 488MHz and a circular shift register with 8K flip-flops and 50K gates. Measurement results indicate that it is possible to reach 24.4x power savings by 6.1x frequency downscaling using AVS, ±24% power and ±22% frequency tuning at nominal conditions using ABB only, 127x power savings with 37.4x frequency downscaling by combining AVS and ABB.

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Abstract-In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13µm triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.

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