Technology exploration for adaptive power and frequency scaling in 90nm CMOS

Abstract

In this paper we examine the expectations and limitations of design technologies such as adaptive voltage scaling (AVS) and adaptive body biasing (ABB) in a modern deep sub-micron process. To serve this purpose, a set of ring oscillators was fabricated in a 90nm triple-well CMOS technology. The analysis hereby presented is based on two ring oscillators running at 822MHz and 93MHz, respectively. Measurement results indicate that it is possible to reach 13.8x power savings by 3.4x frequency downscaling using AVS, ±11% power and ±8% frequency tuning at nominal conditions using ABB only, 22x power savings with 5x frequency downscaling by combining AVS and ABB, as well as 22x leakage reduction.

Limits to Performance Spread Tuning using Adaptive Voltage and Body Biasing

“…The results shown in this paper extend the results in [13] in two ways: (i) we will show results for a power-optimized 90nm CMOS technology, and (ii) we will report V DD and V th scaling ranges to tune process-dependent performance spreads. Section 2 introduces the voltage conventions we used for AVS and ABB.…”

“…In [13] we have already shown the results for the CGU when fabricated in a general-purpose (GP) 90nm CMOS technology with a nominal supply of 1V. The results shown in this paper extend the results in [13] in two ways: (i) we will show results for a power-optimized 90nm CMOS technology, and (ii) we will report V DD and V th scaling ranges to tune process-dependent performance spreads.…”

Runtime identification of microprocessor energy saving opportunities

“…Current microprocessors already have facilities for scaling frequency and voltage [9][1] in order to save power. Unfortunately, existing power scaling policies guarantee safe operating conditions, not optimum efficiency.…”

Testing and Diagnosis of Power Switches in SOCs

“…This, however, will lead to increased leakage power due to increased sub-threshold leakage and gate oxide tunneling current. As feature sizes shrink below 100nm, leakage power becomes as important as dynamic switching power in many applications [1][2] [3]. To minimize both dynamic switching power as well as leakage power dissipation, modern system chips (SOCs) require efficient power management.…”