Testing and Diagnosis of Power Switches in SOCs

Goel, Sandeep; Meijer, Maurice; Gyvez, José Pineda de

doi:10.1109/ets.2006.47

Cited by 26 publications

(26 citation statements)

References 13 publications

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“…Recent research has reported a number of DFT solutions to test power-switches when considering the two possible type of faults: stuck-open and stuck-short [3], [4]. The first DFT solution is reported in [3], and is used to test power switches in both fine-grain and coarse-grain designs (Fig.…”

Section: Introductionmentioning

confidence: 99%

Improved DFT for Testing Power Switches

Khursheed

Yang

Al-Hashimi

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Abstract-Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge this is the first study that analyzes recently proposed DFT solutions for testing power switches through SPICE simulations on a number of ISCAS benchmarks and presents the following contributions. It provides evidence of long discharge time when power switches are turned-off, when testing power switches using available DFT solutions. This may either lead to false test (false-fail or false-pass) or long test time. This problem is addressed through a simple and effective DFT solution to reduce the discharge time. The proposed DFT solution has been validated through SPICE simulation and shows an improvement in discharge time of at least 28-times, based on a number of ISCAS benchmarks synthesized with a 90-nm gate library.Index Terms-Sleep transistor, power switch, leakage power management, test time overhead, DFT, design for test.

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Section: Introductionmentioning

confidence: 99%

Improved DFT for Testing Power Switches

Khursheed

Yang

Al-Hashimi

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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“…In coarse-grain design style, power switches are divided into segments and the number of power switches per segment has a trade-off between area overhead, test time and precision in identifying faulty transistors [5], [9], [10]. This is shown in Table I, where for each design, we varied segment size from 5 to 30, and evaluated diagnosis accuracy using a fixed test frequency.…”

Section: Analysis Of Segment Size and Test Frequencymentioning

confidence: 99%

“…It is critical to silicon debugging, yield analysis and for improving subsequent manufacturing cycle [6]- [8]. Recent research has reported a number of DFT solutions to test power-switches when considering the two possible type of faults: stuck-open and stuck-short [5], [9]- [11]. Stuck-open fault models a physical scenario, where the drain or source of a transistor is disconnected leading to a faulty transistor behavior.…”

mentioning

confidence: 99%

“…Stuck-short faults produce a conducting path between V dd and ground and may be detected by a test technique called I DDQ testing, that monitors the current flow during steady-state condition [7]. The first DFT solution is reported in [9], and is used to test power switches in both finegrain and coarse-grain designs. However, it was highlighted in [10] that this DFT solution suffers from long discharge time when power switches are turned off.…”

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confidence: 99%

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Delay Test for Diagnosis of Power Switches

Khursheed

Shi

Al-Hashimi

et al. 2014

IEEE Trans. VLSI Syst.

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Abstract-Power switches are used as part of power-gating technique to reduce leakage power of a design. To the best of our knowledge, this is the first work in open-literature to show a systematic diagnosis method for accurately diagnosing power switches. The proposed diagnosis method utilizes recently proposed DFT solution for efficient testing of power switches in the presence of PVT variation. It divides power switches into segments such that any faulty power switch is detectable thereby achieving high diagnosis accuracy. The proposed diagnosis method has been validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; and the worst case loss of accuracy is less than 12% when considering VT (Voltage and Temperature) variations.Index Terms-Sleep transistor, diagnosis, power gating, leakage power management, design for test (DFT).

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“…Usually, this is done in sequence and takes some time to get a power domain to its stable state. Many switches are used for given power domain and assembled in "fault-tolerant" scheme [20]. A defective switch (stuck-ON/OFF) usually results in performance degradation.…”

Section: Test Of Power Management Structuresmentioning

confidence: 99%

Test strategies for low power devices

Ravikumar

Hirech

Wen

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the target application, there are stringent guidelines on the number of defective parts per million shipped devices. At the same time, since such devices are cost-sensitive, test cost is a major consideration. Since system-level power-management techniques are employed in these devices, test generation must be powermanagement-aware to avoid stressing the power distribution infrastructure in the test mode. Structural test techniques such as scan test, with or without compression, can result in excessive heat dissipation during testing and damage the package. False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss. This paper considers different aspects of testing low-power devices and some new techniques to address these problems.

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Testing and Diagnosis of Power Switches in SOCs

Cited by 26 publications

References 13 publications

Improved DFT for Testing Power Switches

Improved DFT for Testing Power Switches

Delay Test for Diagnosis of Power Switches

Test strategies for low power devices

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