Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning

Meijer, Maurice; Gyvez, José Pineda de

doi:10.1007/978-0-387-76472-6_2

Cited by 14 publications

(21 citation statements)

References 12 publications

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“…Maurice Meijer 1) , José Pineda de Gyvez 1) 2) , Ben Kup 1) , Bert van Uden 1) , Peter Bastiaansen 1) , Marco Lammers 1) , and Maarten Vertregt Modern digital integrated circuits are sensitive to process variability that impacts circuit performance and power consumption. In recent years, post-silicon tuning has shown to be effective to counteract process variability, or to trade-off power-performance [1][2].…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

“…In recent years, post-silicon tuning has shown to be effective to counteract process variability, or to trade-off power-performance [1][2]. Well-known post-silicon tuning techniques are supply voltage scaling (VS) and body biasing (BB).…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

“…Well-known post-silicon tuning techniques are supply voltage scaling (VS) and body biasing (BB). VS is primarily used to reduce active power at the expense of a lower circuit performance [1]. BB is typically used for leakage reduction or performance tuning [1][2].…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

“…VS is primarily used to reduce active power at the expense of a lower circuit performance [1]. BB is typically used for leakage reduction or performance tuning [1][2]. Two BB approaches exist, namely reverse body bias (RBB) and forward body bias (FBB).…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

“…Contrarily, FBB reduces V th which lowers gate delay at a leakage cost. VS and BB can also be combined to achieve collective benefits [1].…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

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A forward body bias generator for digital CMOS circuits with supply voltage scaling

Meijer

Gyvez

Kup

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Meijer, R.I.M.P.; Pineda de Gyvez, J.; Kup, B.; Uden, van, B.; Bastiaansen, P.; Lammers, M.; Vertregt, M. Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim.

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Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

“…Contrarily, FBB reduces V th which lowers gate delay at a leakage cost. VS and BB can also be combined to achieve collective benefits [1].…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

See 3 more Smart Citations

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Meijer

Gyvez

Kup

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

Self Cite

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Energy efficient scheduling algorithm for the multicore heterogeneous embedded architectures

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Technological Boundaries of Voltage and Frequency Scaling for Power Performance Tuning

Cited by 14 publications

References 12 publications

A forward body bias generator for digital CMOS circuits with supply voltage scaling

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Commercially Viable Ultra-Low Power Wireless

Energy efficient scheduling algorithm for the multicore heterogeneous embedded architectures

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