Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields

Inoue, Katsuro; Takeuchi, Naoki; Narama, Tatsuya; Yamanashi, Yuki; Yoshikawa, Nobuyuki

doi:10.1088/0953-2048/28/4/045020

Cited by 10 publications

(5 citation statements)

References 24 publications

(29 reference statements)

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“…One such effort that should be mentioned is using another family of logic, AQFP, to develop adders with the goal of eventually building a processor. This work has also shown promise and has had some successful demonstrations (Inoue et al, 2013;Inoue et al, 2015;Narama et al, 2015).…”

Section: Superconducting Digital Electronics Developmentmentioning

confidence: 89%

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

Tschirhart

Segall

2021

Front. Neurosci.

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Superconducting electronics (SCE) is uniquely suited to implement neuromorphic systems. As a result, SCE has the potential to enable a new generation of neuromorphic architectures that can simultaneously provide scalability, programmability, biological fidelity, on-line learning support, efficiency and speed. Supporting all of these capabilities simultaneously has thus far proven to be difficult using existing semiconductor technologies. However, as the fields of computational neuroscience and artificial intelligence (AI) continue to advance, the need for architectures that can provide combinations of these capabilities will grow. In this paper, we will explain how superconducting electronics could be used to address this need by combining analog and digital SCE circuits to build large scale neuromorphic systems. In particular, we will show through detailed analysis that the available SCE technology is suitable for near term neuromorphic demonstrations. Furthermore, this analysis will establish that neuromorphic architectures built using SCE will have the potential to be significantly faster and more efficient than current approaches, all while supporting capabilities such as biologically suggestive neuron models and on-line learning. In the future, SCE-based neuromorphic systems could serve as experimental platforms supporting investigations that are not feasible with current approaches. Ultimately, these systems and the experiments that they support would enable the advancement of neuroscience and the development of more sophisticated AI.

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Section: Superconducting Digital Electronics Developmentmentioning

confidence: 89%

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

Tschirhart

Segall

2021

Front. Neurosci.

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“…The dc superconducting quantum interference device (SQUID) part (J 1 -L 1 -L 2 -J 2 ) is placed above the ground plane (M4 of the MIT LL SFQ5ee process), whereas the output signal transformer part (L q and L out ) is placed below the ground plane. This mitigates unwanted couplings between the dc SQUID and the output signal transformer, even without magnetic shields [22]. As a result, the signal transformer can be designed in an asymmetric way to reduce the footprint area; note that conventional design uses symmetrical structures to mitigate unwanted couplings [16,17], which results in a somewhat large cell dimension.…”

Section: Design Of Logic Cellsmentioning

confidence: 99%

“…Ports dcin and dcout are bidirectional ports of the dc offset. The principle operation of the AQFP is described in detail in [11,17,22]. Due to relatively strong intrinsic damping of the SFQ5ee process [20], the junctions J 1 and J 2 are underdamped without shunt resistors to achieve extremely low energy consumption [14].…”

Section: Design Of Logic Cellsmentioning

confidence: 99%

A compact AQFP logic cell design using an 8-metal layer superconductor process

Ayala

Takeuchi

et al. 2020

Supercond. Sci. Technol.

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Adiabatic quantum-flux-parametron (AQFP) is an adiabatic logic based on the quantum-fluxparametron. It has extremely low switching energy, as well as high signal gain and high robustness. In this work, we present the development of an AQFP cell library using the MIT LL 100 μA μm −2 superconductor electronics fabrication process, SFQ5ee. Four types of basic subcells, i.e. buffer, inverter, constant, and branch, are designed as the building blocks for combinational AQFP logic cells. Taking advantage of the 8 metal layers, we place the dc superconducting quantum interference device (SQUID) part of a buffer above the ground plane and the signal transformer part below the ground plane to mitigate unwanted couplings. In addition, by vertically overlapping the signal transformer and the dc SQUID, the dimension of a buffer is reduced to 15 μm × 20 μm, which is only 30% of that of the conventional design. More complex AQFP logic cells, such as the majority gate, AND gate, and OR gate, are designed by arraying the sub-cells together. Correct operations and wide excitation current margins are confirmed for the established AQFP logic cells by both simulation and experiments.

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“…AQFP cell layouts need to be carefully designed to suppress unwanted magnetic coupling between the ac clock line and the output inductance. Therefore, in previous works, we adopted superconductor magnetic shields [12] or symmetric layout [16]. In this study, we use AQFP gates with symmetric layout.…”

Section: Parasitic Coupling In Aqfp Gate With Resistive Branchesmentioning

confidence: 99%

“…Full-gate extraction models that include resistance are becoming more important as process density, layout ingenuity and circuit complexity increase. Circuit operation can be ruined by almost negligible coupling [12] so that reliable full-gate inductance extraction becomes an important pillar of circuit design.…”

Section: Introductionmentioning

confidence: 99%

Inductance and Current Distribution Extraction in Nb Multilayer Circuits with Superconductive and Resistive Components

Fourie

Takeuchi

Yoshikawa

2016

IEICE Trans. Electron.

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SUMMARYWe describe a calculation tool and modeling methods to find self and mutual inductance and current distribution in superconductive multilayer circuit layouts. Accuracy of the numerical solver is discussed and compared with experimental measurements. Effects of modeling parameter selection on calculation results are shown, and we make conclusions on the selection of modeling parameters for fast but sufficiently accurate calculations when calibration methods are used. Circuit theory for the calculation of branch impedances from the output of the numerical solver is discussed, and compensation for solution difficulties is shown through example. We elaborate on the construction of extraction models for superconductive integrated circuits, with and without resistive branches. We also propose a method to calculate current distribution in a multilayer circuit with multiple bias current feed points. Finally, detailed examples are shown where the effects of stacked vias, bias pillars, coupling, ground connection stacks and ground return currents in circuit layouts for the AIST advanced process (ADP2) and standard process (STP2) are analyzed. We show that multilayer inductance and current distribution extraction in such circuits provides much more information than merely branch inductance, and can be used to improve layouts; for example through reduced coupling between conductors.

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Design and demonstration of adiabatic quantum-flux-parametron logic circuits with superconductor magnetic shields

Cited by 10 publications

References 24 publications

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

BrainFreeze: Expanding the Capabilities of Neuromorphic Systems Using Mixed-Signal Superconducting Electronics

A compact AQFP logic cell design using an 8-metal layer superconductor process

Inductance and Current Distribution Extraction in Nb Multilayer Circuits with Superconductive and Resistive Components

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