A compact AQFP logic cell design using an 8-metal layer superconductor process

He, Yuxing; Ayala, Christopher L.; Takeuchi, Naoki; Yamae, Taiki; Hironaka, Yuki; Sahu, Anubhav; Gupta, Varun; Talalaevskii, Andrei; Gupta, Deepnarayan; Yoshikawa, Nobuyuki

doi:10.1088/1361-6668/ab6feb

Cited by 21 publications

(6 citation statements)

References 26 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This can reduce the cell size in half but unlike conventional AQFP cells, the DQFP buffer and inverter have different core structures, introducing complexities in cell library development. Another approach is to use a more advanced process with more layers [23]- [25]. With more layers, the transformer and the SQUID can be stacked vertically, roughly halving the footprint of the logic cell.…”

Section: Scaling Of the Aqfp Ksamentioning

confidence: 99%

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

Tanaka

Ayala

Yoshikawa

2022

IEICE Trans. Electron.

Self Cite

View full text Add to dashboard Cite

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of energy-efficient logic families. Among them is the adiabatic quantum-flux-parametron (AQFP) logic family, which adiabatically switches the quantum-flux-parametron (QFP) circuit when it is excited by an AC power-clock. When compared to stateof-the-art CMOS technology, AQFP logic circuits have the advantage of relatively fast clock rates (5 GHz to 10 GHz) and 5 -6 orders of magnitude reduction in energy before cooling overhead. We have been developing extremely energy-efficient computing processor components using the AQFP. The adder is the most basic computational unit and is important in the development of a processor. In this work, we designed and measured a 16-bit parallel prefix carry look-ahead Kogge-Stone adder (KSA). We fabricated the circuit using the AIST 10 kA/cm 2 High-speed STandard Process (HSTP). Due to a malfunction in the measurement system, we were not able to confirm the complete operation of the circuit at the low frequency of 100 kHz in liquid He, but we confirmed that the outputs that we did observe are correct for two types of tests: (1) critical tests and (2) 110 random input tests in total. The operation margin of the circuit is wide, and we did not observe any calculation errors during measurement.

show abstract

Section: Scaling Of the Aqfp Ksamentioning

confidence: 99%

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

Tanaka

Ayala

Yoshikawa

2022

IEICE Trans. Electron.

Self Cite

View full text Add to dashboard Cite

show abstract

“…This is partly because of the design methodology of using only a single-clock phase per row of logic and the large logic cell size due to the output transformer of the AQFP. We have already shown promising work on using a more advanced eight-layer superconductor IC fabrication process provided by MIT Lincoln Laboratory, Lexington, MA, USA [41] to create a more compact AQFP cell library [42]. We can also potentially remove the large output transformer completely by using directly coupled QFP (DQFP) [43].…”

Section: A Area Efficiencymentioning

confidence: 99%

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices

Ayala

Tanaka

Saito

et al. 2021

IEEE J. Solid-State Circuits

Self Cite

View full text Add to dashboard Cite

We conducted the first successful demonstration of an adiabatic microprocessor based on unshunted Josephson junction (JJ) devices manufactured using a Nb/AlO x /Nb superconductor IC fabrication process. It is a hybrid of RISC and dataflow architectures operating on 4-b data words. We demonstrate register file R/W access, ALU execution, hardware stalling, and program branching performed at 100 kHz under the cryogenic temperature of 4.2 K. We also successfully demonstrated a highspeed breakout chip of the microprocessor execution units up to 2.5 GHz. We use a logic primitive called the adiabatic quantumflux-parametron (AQFP), which has a switching energy of 1.4 zJ per JJ when driven by a four-phase 5-GHz sinusoidal ac-clock at 4.2 K. These demonstrations show that AQFP logic is capable of both processing and memory operations and that we have a path toward practical adiabatic computing operating at highclock rates while dissipating very little energy.

show abstract

“…For instance, the SFQ cell library developed recently under the IARPA Supertools program [11] has device number density of only 5•10 5 Josephson junctions (JJs) per cm 2 , i.e., a factor of 30 lower than what the fabrication technology is capable to provide [12], [13]. The existing cell libraries of superconductor adiabatic circuits based on Adiabatic Quantum Flux Parametrons (AQFP) provide similarly low device number densities: about 4.8 •10 5 JJs/cm 2 [14], [15] for the SFQ5ee fabrication process at MIT LL [16], [17]; and about 1.6•10 5 JJs/cm 2 [18], [19] for the fabrication process developed at AIST, Japan. These device densities are almost five orders of magnitude lower than those in CMOS circuits.…”

Section: Introductionmentioning

confidence: 99%

Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in a Planarized Fabrication Process With Nb Ground Planes

Tolpygo

Golden

Weir

et al. 2023

IEEE Trans. Appl. Supercond.

View full text Add to dashboard Cite

To increase integration scale of superconductor electronics, we are developing a new node, titled SFQ7ee, of the fabrication process at MIT Lincoln Laboratory. In comparison to the existing SFQ5ee node, we increased the number of fully planarized superconducting layers to ten and utilized NbN and NbN/Nb kinetic inductors to increase the possible inductor number density above a hundred million inductors per cm 2 . Increasing the Josephson junction number density to the same level requires implementing self-shunted high-Jc Josephson junctions. We investigated properties of Nb/NbNx/Nb trilayer junctions as a potential replacement of high-Jc Nb/Al-AlOx/Nb junctions, where NbNx is a disordered, overstoichiometric, nonsuperconducting nitride deposited by reactive sputtering. Dependences of the IcRn product and Josephson critical current density, Jc on the NbNx barrier thickness and on temperature were studied in the thickness range from 5 nm to 20 nm. The fabricated junctions can be well described by the microscopic theory of SNS junctions, assuming no suppression of the energy gap in Nb electrodes near the NbNx interfaces and a Cooper pair decay length in the NbNx barrier, 𝝃𝝃 𝒏𝒏 (𝑻𝑻 𝒄𝒄 ), of about 2.3 nm. Currentvoltage characteristics of the junctions are well described by the resistively and capacitively shunted junction (RCSJ) model without excess current. In the studied range Jc < 10 mA/µm 2 , the Nb/NbNx/Nb junctions have lower values of the specific resistance RnA, lower IcRn products, and a stronger dependence of the IcRn on temperature than the self-shunted or critically damped externally shunted Nb/Al-AlOx/Nb junctions with the same critical current density; A is the junction area, Ic the junction critical current, and Rn the effective shunting resistance.

show abstract

A compact AQFP logic cell design using an 8-metal layer superconductor process

Cited by 21 publications

References 26 publications

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

A 16-Bit Parallel Prefix Carry Look-Ahead Kogge-Stone Adder Implemented in Adiabatic Quantum-Flux-Parametron Logic

MANA: A Monolithic Adiabatic iNtegration Architecture Microprocessor Using 1.4-zJ/op Unshunted Superconductor Josephson Junction Devices

Self- and Mutual Inductance of NbN and Bilayer NbN/Nb Inductors in a Planarized Fabrication Process With Nb Ground Planes

Contact Info

Product

Resources

About