Data retention under gate stress on a NVM array

Djenadi, R.; Micolau, G.; Postel-Pellerin, J.; Chiquet, P.; Laffont, R.; Ogier, Jean-Luc; Régnier, A.; Lalande, F.; Melkonian, J.

doi:10.1016/j.sse.2012.06.006

Cited by 6 publications

(3 citation statements)

References 11 publications

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“…Moreover, this positive bias will decrease the floating gate potential according to Eq. (2), also reducing the charge leakage as demonstrated in [15]. We will detail the integration of these microbatteries in Section 3.…”

Section: Contents Lists Available At Sciencedirectmentioning

confidence: 99%

A new non-volatile memory architecture embedding microbatteries to improve data retention criterion

Postel-Pellerin

Chiquet

Lalande

2014

Solid-State Electronics

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Section: Contents Lists Available At Sciencedirectmentioning

confidence: 99%

A new non-volatile memory architecture embedding microbatteries to improve data retention criterion

Postel-Pellerin

Chiquet

Lalande

2014

Solid-State Electronics

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“…The Cell Array Stress Test (CAST) is a very useful vehicle to study reliability of charge storage memory cells since the 1990s [1]. It provides for example the possibility to detect overerased bit tails or weaknesses in terms of data retention [2,3]. Furthermore, the problems due to the access resistance of a cell in a memory array can be modeled to optimize the number of contacts to bring the voltage biasing in a specific area without loss [4].…”

Section: Introductionmentioning

confidence: 99%

SuperCAST: a full free addressable memory array

Marca

Guilleau-Tavernier

Laine

et al. 2022

2022 IEEE 34th International Conference on Microelectronic Test Structures (ICMTS)

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In this paper we present a full free addressable 4kb EEPROM memory array. This test structure based on CAST vehicle has been upgraded with flexible addressing logic to select any numbers of cells on single or multiple word lines. To this aim, column/row shift registers, to enable an easy cell biasing, have been implemented in an embedded non-volatile memory environment. High voltage circuits, driven by low voltage shift registers, are used to bias selected cells for electrical characterizations and reliability tests purposes. This kind of structure has been developed to improve the efficiency of electrical characterization laboratory, resulting in an enhanced acquisition with respect to standard CAST test techniques, opening the path to fine statistical analysis.

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“…In this paper, we propose a method to model the drain current-gate voltage (I D -V G ) characteristics of a memory cells array using the results obtained on a 512kB test chip. The aim is to predict the distribution of memory cells inside a cell array stress test [1,2] and its shape (intrinsic and extrinsic population as in [3] or [4]) with a single I D -V G characteristic. The measurement are in general impacted by the test structure design [5,6], thus to reach the goal, we considered the contribution of the CAST access resistance.…”

Section: Introductionmentioning

confidence: 99%

A new method for test chip and single 40nm NOR Flash cell electrical parameters correlation using a CAST structure

Kempf

Marca

Canet

et al. 2018

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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In this work we present a method to find a correlation between the measurements on single 40nm embedded Flash memory cell, and the 512kB test chip electrical results. The bridge between these two structures is the cell array stress test (CAST). We are able to simulate the behavior of a 10kb and a 1Mb CAST structures. The parasitic resistances are taken into account, as well as, the testchip distributions for the modeling. The aim is to reduce the time of test obtaining preliminary information concerning the fabrication process and the memory yield at the parametric test level and before the electrical wafer sorting.

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Data retention under gate stress on a NVM array

Cited by 6 publications

References 11 publications

A new non-volatile memory architecture embedding microbatteries to improve data retention criterion

A new non-volatile memory architecture embedding microbatteries to improve data retention criterion

SuperCAST: a full free addressable memory array

A new method for test chip and single 40nm NOR Flash cell electrical parameters correlation using a CAST structure

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