Conformal and Ultra Shallow Junction Formation Achieved Using a Pulsed-Laser Annealing Process Integrated With a Modified Plasma Assisted Doping Method

Baik, Seunghun; Kwon, Dong-Jae; Kang, Hongki; Jang, Jae Eun; Jang, Jaewon; Kim, Y. S.; Kwon, Hyuk‐Jun

doi:10.1109/access.2020.3024636

Cited by 8 publications

(4 citation statements)

References 43 publications

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“…Plasma doping is designed for high-dose ultra-low energy or high-aspect-ratio structure doping. It has been proven to be effective in forming ultra-shallow junctions; the whole wafer was immersed in dopant-contained plasma to obtain a conformal doping profile [212][213][214][215]. However, as there was a bias in the PLAD system to accelerate the ions, the maximum doping concentration still appears on the top area of the device and leads to nonuniform distribution.…”

Section: Plasma Dopingmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Plasma Dopingmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…Although new structures such as the 'FIN' gate have been widely adopted in modern CMOS transistors to address this issue [4,5], it is still essential to have ultrashallow doping in source and drain to alleviate the short channel effect. For this reason, doping techniques to form ultrashallow junctions (USJs) have been extensively explored in the past decades [6][7][8][9][10][11][12]. In addition to classical CMOS transistors, ultrashallow doping has also found applications in deterministic doping at atomic scale for quantum-computing [13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Advances in ultrashallow doping of silicon

Zhang

Chang

Dan

2021

Advances in Physics: X

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Ultrashallow doping is required for both classical field-effect transistors in integrated circuits and revolutionary quantum devices in quantum computing. In this review, we give a brief overview on recent research advances in three technologies to form ultrashallow doping, namely molecular monolayer doping, molecular beam epitaxy, and low energy ion implantation. A research perspective will be provided at the end of this review.

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“…Ultra-shallow junctions have a wide application in modern semiconductor devices such as metal-oxide-semiconductor transistors, photodiodes and x-ray detectors [1][2][3]. As complementary metal-oxide-semiconductor transistor devices scale down to sub-10 nm, ultra-shallow junctions with a depth of less than 5 nm will be required [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Fabrication of ultra-shallow junction by in situ doped amorphous silicon films and its application in silicon drift detectors

Jiang¹,

Jia²,

Tao³

et al. 2021

J. Phys. D: Appl. Phys.

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In situ doped amorphous silicon film, deposited by plasma enhanced chemical vapor deposition, is employed as a diffusion source to form an ultra-shallow junction and as voltage dividers in silicon drift detectors. By controlling annealing temperature and time, the junction depth can be adjusted precisely, and the shallowest junction depth of 15 nm is achieved. The I-V characteristics of the ultra-shallow junction, fabricated with different annealing temperature, annealing time and doping concentration, are then analyzed, and the reverse leakage current can be reduced to as low as 2 nA cm −2 under a reverse bias of 200 V at room temperature. The doped silicon film is also used to fabricate voltage dividers in silicon drift detectors. The sheet resistance of the silicon film is adjusted by controlling the thickness and annealing conditions, and a high resistance value and small temperature coefficient of the voltage dividers are achieved. Finally, the in situ doped amorphous silicon film is used to fabricate silicon drift detectors and the final energy resolution of 180 eV at 5.9 keV is achieved.

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Conformal and Ultra Shallow Junction Formation Achieved Using a Pulsed-Laser Annealing Process Integrated With a Modified Plasma Assisted Doping Method

Cited by 8 publications

References 43 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Advances in ultrashallow doping of silicon

Fabrication of ultra-shallow junction by in situ doped amorphous silicon films and its application in silicon drift detectors

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