Concurrent transient fault simulation for analog circuits

Hou, Junwei; Chatterjee, Abhijit

doi:10.1109/tcad.2003.818129

Cited by 20 publications

(6 citation statements)

References 22 publications

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“…While the simulation of analog circuits impacts the current and voltage levels across all the branches and circuit nodes. Concurrent [51] and parallel fault simulation [37] are considered efficient tools for fault simulation for digital circuits. Nevertheless, fault simulation in analog circuits is often achieved by repeating the process of injecting the defects systematically, requiring to consume a lot of time.…”

Section: Concurrent and Parallel Fault Simulationmentioning

confidence: 99%

“…This technique also provides better performance because the simulation allows the reuse of some results and structures which are obtained from the previous runs [30], [43]. In another paper [51], an efficient fault simulation method has been proposed to simulate defects with a DC and transient simulation simultaneously. The division of the fault groups is dynamic depending on their impact on transient response.…”

Section: Concurrent and Parallel Fault Simulationmentioning

confidence: 99%

See 1 more Smart Citation

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Azam

Dall'Ora

Fraccaroli

et al. 2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field.Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions.

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Section: Concurrent and Parallel Fault Simulationmentioning

confidence: 99%

Section: Concurrent and Parallel Fault Simulationmentioning

confidence: 99%

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Azam

Dall'Ora

Fraccaroli

et al. 2024

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

View full text Add to dashboard Cite

show abstract

“…Computation rules are difficult to derive for complex gates and gate delays are difficult to use. Concurrent fault simulation is based on the observation that most values in most of the faulty circuits match the corresponding values in the good circuit [10]. Information about a fault will be entered in the fault list if at least one input or output of the gate is different from that implied at the corresponding line in the fault free version of the circuit.…”

Section: Related Workmentioning

confidence: 99%

Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern

Šeinauskas

Cvirka

Rudžionienė

2015

ElAEE

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A new fault simulation procedure is suggested. The procedure provides fault detection of individual test patterns at the beginning. In this way, most faults are detected quickly. The remaining faults are analysed by conventional means with a sequence of test patterns. Creation of individual fault lists of test patterns allows speeding up the fault simulation. The fault simulation acceleration increases with circuit size and test coverage.

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“…When the loop settles the voltage at the output of the adder ( adder V ) approaches to zero and according to (6), cnt V can be represented by:…”

Section: Bist Architecture and Operationmentioning

confidence: 99%

“…The problem of testing the analog cores of mixed signal ICs has been considered by a number of researchers [1,5,6,7]. However, testing mixed signal systems still is a major challenge due to the growing SoC complexity and increasing operating frequencies.…”

Section: Introductionmentioning

confidence: 99%

A PLL based analog core tester

Rashidzadeh

Miller

Ahmadi

Canadian Conference on Electrical and Computer Engineering, 2005.

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A novel architecture for testing the analog cores of a mixed signal System-on-Chip (SoC) has been proposed. A Phase Locked Loop (PLL) has been modified to enable an accurate analog Built-In Self-Test (BIST) capability. The specified phase and amplitude response of the Circuit-Under-Test (CUT) are represented as a test control voltage that determines the lock condition for the PLL based tester. The test control voltage locks the PLL depending on the frequency response of the CUT. Faults are detected either by the PLL not locking or by determining that the locking frequency is not the nominal value for a fault free CUT. The proposed tester has capabilities to test high frequency analog circuits. Experimental results demonstrate the effectiveness of the proposed method.

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Concurrent transient fault simulation for analog circuits

Cited by 20 publications

References 22 publications

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern

A PLL based analog core tester

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