No abstract

Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based on experimental results, we developed a framework of delay test generation for non-scan sequential circuits. The provided comparison with experimental results of other approaches demonstrates the effectiveness of proposed framework. Bibl. 13, tabl. 4 (in English; abstracts in English and Lithuanian).http://dx.doi.org/10.5755/j01.eee.109.3.173

The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the representation of the function of the circuit. The faults are considered on the inputs and on the outputs of the model only. The random input stimuli are generated and selected then according to the proposed approach. The experimental results demonstrate the superiority of the delay test stimuli generated at the functional level using the introduced approach against the transition test stimuli obtained at the gate level by deterministic test generator. The functional delay test generation approach especially is useful for the circuits, when the long test sequences are needed in order to detect transition faults.

No abstract

No abstract

A discussion has been held on the application of (distance education at the CAD Laboratory of the Kaunas University of Technology. Modern capabilities of the .Internet open the ways of using any CAD system via any (computer, connected to the Internet. Three levels of communications are discussed. A distance laboratory uses speclJic adapted methods, re-formulated laboratory $exercises and a special software. Project-based education is very valuable by self-studying and for continuing (education. The verfication has now become very important to Jinishing an electronic design project. A special sofiware of registering saves time of the professors. Laboratory exercises of electronic design use widely configurable field-programmable gate arrays (FPGA). At present, such exercises can be done via a ,@etwork. Some initial collection of practical laboratory (exercises of design system CADENCE was prepared, performed and tested. The principles suggested can be (extended to other objects of teaching, and introduce important changes in teaching practices of the future.

No abstract

The aim of this paper is to explore some features of the functional test generation problem, and on the basis of the gained experience, to propose a practical method for functional test generation. In the paper presented analysis of random search methods and adjacent stimuli generation allowed formulating a practical method for generating functional tests. This method incorporates the analyzed termination conditions of generation, exploits the advantages of random and deterministic search, as well as the feature that the sets of the selected input stimuli can be merged easily in order to obtain a better set of test patterns.