Functional fault models for non-scan sequential circuits

Bareiša, Eduardas; Jusas, Vacius; Motiejūnas, Kęstutis; Šeinauskas, Rimantas

doi:10.1016/j.microrel.2011.07.069

Cited by 5 publications

(19 citation statements)

References 17 publications

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“…Functional delay test sequences can be produced using functional delay fault models described in [2], [3], [4], [5], [6], [7]. In this case, test generation usually targets a specific fault model to ensure that the sequences are effective to detect delay faults at the gate level of the circuit.…”

Section: Related Workmentioning

confidence: 99%

“…The experimental results were presented for two small circuits only. Next, Bareiša et al [4] presented an approach of test generation for non-scan synchronous sequential circuits using functional delay fault models. The software prototype model was used for definition of the function of the circuit.…”

Section: Related Workmentioning

confidence: 99%

“…The idea of functional delay fault models [4] was explored further and developed in [5]. The goal of the research was the efficiency of the implementation of the models, which was expressed in the obtained delay fault coverage and required computation time.…”

Section: Related Workmentioning

confidence: 99%

“…In order to improve the performance of test generation Bareisa et al [6] suggested a method for functional delay test generation. The method consists of two following stages: preliminary test selection and functional test generation based on fault simulation [5]. The goal of the first stage is to minimize the number of test sequences considered during the second stage.…”

Section: Related Workmentioning

confidence: 99%

“…Functional delay fault models based on the primary inputs, primary outputs, and state variables of the circuit have been successfully used for test generation [2], [3], [4], [5], [6], [7]. Functional delay fault model is based on the stuck-at fault pairs at the primary inputs, primary outputs and state variables.…”

Section: Introductionmentioning

confidence: 99%

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Black box delay fault models for non-scan sequential circuits

et al. 2018

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We presented nine new black box delay fault models for non-scan sequential circuits at the functional level, when the primary inputs and primary outputs are available only. We examined the suggested fault models in two stages. During the first stage of the experiment, we selected the best two fault models for further examination on the base of criterion proposed in the paper. During the second stage, we used the functional delay fault model and two black box delay fault models from the first stage for test selection. The comparison of fault coverages was carried out for transition faults. The obtained results demonstrate that transition fault coverages of tests selected based on proposed black box fault models are similar to coverages of tests selected based on functional delay fault model that uses the inner state of circuit.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Black box delay fault models for non-scan sequential circuits

et al. 2018

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Evaluation of testability enhancement using software prototype

Bareiša

Jusas

Motiejūnas

et al. 2012

IET Comput. Digit. Tech.

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Path delay test generation at functional level

Bareiša

Jusas

Motiejūnas

et al. 2015

IET Computers & Digital Techniques

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The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

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Functional fault models for non-scan sequential circuits

Cited by 5 publications

References 17 publications

Black box delay fault models for non-scan sequential circuits

Black box delay fault models for non-scan sequential circuits

Evaluation of testability enhancement using software prototype

Path delay test generation at functional level

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