Path delay test generation at functional level

Abstract

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

Formal verification methodology for real‐time Field Programmable Gate Array

“…FPGA‐based real‐time system design and control is a very active area of development and research in both industry and academia [5, 6]. The predominant approach used in industry to check for system (hardware or software) errors is testing [7, 8]. Testing is very effective in finding bugs, but cannot show the absence of bugs.…”