Functional delay test generation based on software prototype

Bareiša, Eduardas; Jusas, Vacius; Motiejūnas, Kęstutis; Šeinauskas, Rimantas

doi:10.1016/j.microrel.2009.06.050

Cited by 7 publications

(5 citation statements)

References 8 publications

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“…A similar idea is used to generate functional delay tests for hardware, using a software prototype [11,12]. The test generation process is used to find as much input and output connectivity as possible.…”

Section: A Brief Overview Of the Most Important Trends In Hardware Anmentioning

confidence: 99%

Examination of the Possibilities for Integrated Testing of Embedded Systems

Šeinauskas¹

2013

AJESA

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Separate testing of hardware and software of embedded systems is insufficient. Communication between hardware and software parts needs to be tested during the integrated testing. Discussions about this problem are practically unavailable. Black-box criteria are used for hardware and software testing. This creates the conditions for formulating a unified test generation task and a single template for the generation of tests, as well as enabling a comparison between the criteria of test generation. Black-box criteria make it possible to start generating tests in the early design stages, once the initial software prototype is established. The test object is described in a finite state machine form. The availability of state variables enables the search for a compromise between test performance and quality in test generation. Experiments with two benchmarks showed which criterion of the black box approach is the most suitable for hardware and software testing and that the generation of integration tests according to two criteria is appropriate. The results are important for choosing a reasonable approach to embedded system integration testing.

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Section: A Brief Overview Of the Most Important Trends In Hardware Anmentioning

confidence: 99%

Examination of the Possibilities for Integrated Testing of Embedded Systems

Šeinauskas¹

2013

AJESA

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“…Such method operates under more difficult conditions, as there is no knowledge of the inner circuit wiring and elements [6][7][8][9][10]. Therefore, separate elements, gates, flip-flops may not be analysed, joined into groups or removed as suggested by other researchers.…”

Section: Previous Work and Experiments Pre-conditionsmentioning

confidence: 99%

“…Both methods have their advantages and disadvantages. [1][2][3][4][5][6][7][8][9][10][11][12] An initializing sequence may not exist, be too long, or set a circuit into an undesired state [1][2][3][4]. Using scan allows easy flip-flop setting, but also increases chip size due to direct access requirement.…”

Section: Introductionmentioning

confidence: 99%

Verification of Initialization Sequences for Sequential Circuits

Morkūnas

Šeinauskas

2011

ElAEE

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This article suggests an approach for verification of initializing sequences. Such sequences were discovered using circuit emulating software prototypes. Software prototypes operate using bivalent logics (0 and 1), while hardware testing employs ternary logic (0, 1 and X). Experimental results show, that validation using ternary logic is too strict, labeling good initializing sequences as bad ones. Experimental results are based on ISCAS'89 benchmark. Ill. 1, bibl. 12, tabl. 3 (in English; abstracts in English and Lithuanian). K. Morkūnas, R. Šeinauskas. Mikroschemų sekų nustatymo verfikavimas // Elektronika ir elektrotechnika. -Kaunas: Technologija, 2011. -Nr. 6(112). -P. 61-64.Šiame straipsnyje pasiūlytas mikroschemų nustatymo sekų verifikavimo metodas. Tokios sekos buvo gautos naudojant mikroschemas imituojančius programinės įrangos prototipus. Prototipai operuoja naudodami dvireikšmę logiką (0 ir 1), kai, testuojant sintezuotas schemas, galima naudoti trireikšmę logiką (0, 1 ir X). Eksperimentų rezultatai rodo, kad trireikšmė logika yra per griežta ir atmeta teisingas nustatymo sekas kaip klaidingas. Eksperimento rezultatai pagrįsti ISCAS'89 testinių mikroschemų rinkiniu. Il. 1, bibl. 12, lent. 3 (anglų kalba; santraukos anglų ir lietuvių k.).

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“…Functional delay testing is preferred to the structural delay testing, because the functional testing assumes at-speed testing. Functional tests can be prepared early in the hardware development life cycle [4]. The circuit designer can prepare manually a functional test according to the specification in order to verify the functionality of the design.…”

Section: Introductionmentioning

confidence: 99%

Path delay test generation at functional level

Bareiša

Jusas

Motiejūnas

et al. 2015

IET Computers & Digital Techniques

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The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

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Functional delay test generation based on software prototype

Cited by 7 publications

References 8 publications

Examination of the Possibilities for Integrated Testing of Embedded Systems

Examination of the Possibilities for Integrated Testing of Embedded Systems

Verification of Initialization Sequences for Sequential Circuits

Path delay test generation at functional level

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