Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern

Šeinauskas, Rimantas; Cvirka, Ramunas; Rudžionienė, Greta

doi:10.5755/j01.eee.21.3.5774

Cited by 1 publication

(1 citation statement)

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“…Generally, the checkability of a digital circuit is defined as its suitability for performing logical checking, which is considered as the possibility of detecting a fault, using for this the error of the result calculated at the output of this circuit in testing or operating mode [7,8].…”

Section: Related Work Goal and Structure Of The Papermentioning

confidence: 99%

Power-Consumption-Oriented Checkability for Fpga-Based Components of Safety-Related Systems

Drozd¹,

Antoniuk²,

Drozd³

et al. 2019

IJC

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This paper is dedicated to the problem of the circuit checkability of components in the safety-related systems, which operate objects of the increased risk and are aimed at ensuring safety of both a system and a control object for accident prevention and a decrease in their consequences. Importance of the checkability of the circuits for ensuring safety in critical applications is emphasized as safety is based on the use of fault tolerant circuitry decisions and their efficiency is defined by the circuit checkability. Development of a logical checkability from testability to structurally functional and dual-mode model which formalizes a problem of the hidden faults and defines ways of its solution is shown. The limitation of a logical checkability in detection of faults in chains of the common signals and the need for development of checkability out of the limits of a logical form, including suitability to checking the circuits on the basis of their power consumption is considered. Power-consumption-oriented checkability (Power-checkability) allowing detection of faults in chains of the common signals is defined. Its analytical assessment for the circuits implemented in FPGA is offered. Experiments providing estimation of power-checkability for FPGA-implementation of iterative array multipliers with various activities of input signals are carried out.

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Section: Related Work Goal and Structure Of The Papermentioning

confidence: 99%