The article is devoted to the problem of checkability of the circuits as an essential element in ensuring the functional safety of informational and control safety-related systems that monitoring objects of increased risk in the energy, transport, military, space and other industries to prevent accidents and reduce their consequences occurrence.The key role of checkabilityin the transformation of fault-tolerant structures used in such systems into fail-safe ones is noted. The problems of logical checkabilityare shown, including the problem of hidden faults, inherent for safety-related systems in the modern design of its components using matrix structures. It was proposed to supplement logical checkabilitywith other forms, among which the most promising are power-oriented checkability, supported by the successful development of green technologies in FPGA (Field Programmable Gate Array) design. The problems of limited accuracy in the assessment and measurement of temperature, which manifested themselves in the development of thermal testability and thermal methods for monitoring circuits, are noted. The lower and upper power-oriented checkability of the circuits is determined by the current consumption parameter. Analytical estimates of the lower and upper checkability of the circuits by current consumption were obtained considering the peculiarities of their design on FPGA using modern CAD (Computer-Aided Design) using the example of Quartus Prime Lite 18.1. The threshold values of consumption currents in the methods of monitoring circuits for detecting faults in the chains of common signals and short-circuit faults within the framework of the lower and upper checkability are estimated, respectively. Experiments have been performed, to evaluate the lower and upper power-oriented checkability of the circuits and threshold values for the presented monitoring methods, using the example of a scalable circuit of the shifting register, designed for FPGA. The dependences of the power-oriented lower and upper checkability of the circuits on the occupancy of the FPGA chip are shown.
In this paper we present logarithmic checking method for on-line testing of the fixed-point adder, multiplier and divider for processing of the approximated data. The check code as logarithmic estimation of fixed-point number is defined. Check equations, connected check codes of operands and result for operation of addition multiplication and division are proved. The method distinguishes errors, which are essential and non-essential for reliability of calculated results. It allows to lower rejection of authentic results and to raise results check reliability in processing of the approximated data in comparison with the residue checking.
The article is devoted to analysis of problems of the computer system development in the domain of critical applications. The main trends of this development were highlighted, which consisted in increased demands for performance based on parallelization of calculations, processing of approximate data and ensuring functional safety in accordance with the need for structuring for parallelism and fuzziness of the natural world, as well as with increased responsibility in decisions made. Analysis of problems encountered in implementation of existing solutions was carried out. There was a lag behind theories limited by the model of exact data from the practice of processing approximate data for modern systems receiving initial data from sensors, including safety-related systems. The problems of matrix structures, which underlie the design of modern computer systems and demonstrate low efficiency in performance and power consumption, as well as in providing functional safety, important for critical applications, are disclosed. The application of fault-tolerant solutions as the basis of functional safety and distrust of these solutions, which is manifested in the practice of using dangerous imitation modes, were noted. They recreate emergency conditions to improve the checkability in solving the problem of hidden faults, since a fault-tolerant solution does not become fail-safe when there is a shortage of checkability. An analysis was given to the sources of the problems considered and the possibilities of solving them from the point of view of a resource-based approach, which identifies the problem of hidden faults as a challenge of growth with a lag of components from the development of the system. The role of matrix structures in the backlog of components and the need to solve the problem by repeating the version redundancy for these structures are shown. Method of introduction of version redundancy into matrix structure on the basis of strongly connected versions for solution of problems of fault tolerance and checkability in complex is proposed. The effectiveness of the method is estimated on an example of the iterative array multiplier using its software model.
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