A PLL based analog core tester

Abstract

A novel architecture for testing the analog cores of a mixed signal System-on-Chip (SoC) has been proposed. A Phase Locked Loop (PLL) has been modified to enable an accurate analog Built-In Self-Test (BIST) capability. The specified phase and amplitude response of the Circuit-Under-Test (CUT) are represented as a test control voltage that determines the lock condition for the PLL based tester. The test control voltage locks the PLL depending on the frequency response of the CUT. Faults are detected either by the PLL not locking or by determining that the locking frequency is not the nominal value for a fault free CUT. The proposed tester has capabilities to test high frequency analog circuits. Experimental results demonstrate the effectiveness of the proposed method.