Comprehensive modeling of NAND flash memory reliability: Endurance and data retention

Xia, Zeyang; Kim, Dae Sin; Jeong, Na-Rae; Kim, Young-Gu; Kim, Jae-Ho; Lee, Keun-Ho; Park, Young-Kwan; Chung, Chee Won; Lee, Hwan; Han, Jong-Seob

doi:10.1109/irps.2012.6241922

Cited by 33 publications

(12 citation statements)

References 7 publications

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“…We propose that the influence of data retention is the main cause for the difference of Tco. Charge loss is usually derived from the direct tunneling, trap assisted tunneling, carrier recombination and diffusion [16], which would distinctively increase at high temperature. Fig.…”

Section: Theoretical Inferencementioning

confidence: 99%

Experimental Investigation of Threshold Voltage Temperature Effect During Cross-Temperature Write–Read Operations in 3-D NAND Flash

You

Wang³

et al. 2021

IEEE J. Electron Devices Soc.

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Reading data at a temperature which different from writing can cause a large number of failed bits in 3D NAND Flash memory. In this work, the threshold voltage(Vth) temperature effect of 3D NAND flash memory cell was investigated and a method was proposed to optimize its temperature coefficient(Tco). The results suggested that the Tco of low temperature programmed high temperature read is larger than high temperature programmed low temperature read and this difference is about 2-3mv/℃, which makes against the temperature compensation of reading voltage and lead to irreparable data errors even there is error correction codes. Furthermore, the critical factor of this difference was demonstrated that is the charge loss during low temperature programmed high temperature read and the Vth shift caused by charge loss is up to 30 percent. Based on this, we proposed to optimize the Tco consistency by shortening the interval time of erase to program in endurance cycling stage and confirmed that this method is effective by experiment. As the time interval becomes smaller, the difference of the Tco decreases as well, which have great reference signification for improving the reliability of 3D NAND flash memory.

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Section: Theoretical Inferencementioning

confidence: 99%

Experimental Investigation of Threshold Voltage Temperature Effect During Cross-Temperature Write–Read Operations in 3-D NAND Flash

You

Wang³

et al. 2021

IEEE J. Electron Devices Soc.

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“…Therefore, for better accuracy, AEP-LDPC (1.086 x 1.187 x 0.991 x 1.006 separates data-retention at RT into two regions, long, when data-retention is dominant, and short, which includes both the effects of data-retention and program-disturb. Moreover, the data-retention effect can be accelerated due to the thermal emission at high temperature conditions [24]. Since the region which includes both data-retention and program-disturb is extremely short at the high temperature [23], the short term effect can almost be ignored.…”

Section: Cell-error Rate (Cer) Parameter Calculation (Unit 3)mentioning

confidence: 99%

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Tokutomi

Tanakamaru

Iwasaki

et al. 2015

Solid-State Electronics

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a b s t r a c tTo improve the reliability of NAND Flash memory based solid-state drives (SSDs), error-prediction LDPC (EP-LDPC) has been proposed for multi-level-cell (MLC) NAND Flash memory (Tanakamaru et al., 2012(Tanakamaru et al., , 2013, which is effective for long retention times. However, EP-LDPC is not as effective for triple-level cell (TLC) NAND Flash memory, because TLC NAND Flash has higher error rates and is more sensitive to program-disturb error. Therefore, advanced error-prediction LDPC (AEP-LDPC) has been proposed for TLC NAND Flash memory (Tokutomi et al., 2014). AEP-LDPC can correct errors more accurately by precisely describing the error phenomena. In this paper, the effects of AEP-LDPC are investigated in a 2Ânm TLC NAND Flash memory with temperature characterization. Compared with LDPC-with-BER-only, the SSD's data-retention time is increased by 3.4Â and 9.5Â at room-temperature (RT) and 85°C, respectively. Similarly, the acceptable BER is increased by 1.8Â and 2.3Â, respectively. Moreover, AEP-LDPC can correct errors with pre-determined tables made at higher temperatures to shorten the measurement time before shipping. Furthermore, it is found that one table can cover behavior over a range of temperatures in AEP-LDPC. As a result, the total table size can be reduced to 777 kBytes, which makes this approach more practical.

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“…However, poly-Si contains high density of dangling bonds (DBs) at both grain boundaries and tunnel oxide/poly-Si interface. These DBs act as carrier traps and lead to the degradation on both cell performance [5][6][7] and reliability [8]. For this reason, in 3D NAND fabrication, a passivation process is necessary to remove these traps by using hydrogen species (H) [9][10].…”

Section: Introductionmentioning

confidence: 99%

Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory

Shen

Xia

Yang

et al. 2020

IEEE J. Electron Devices Soc.

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Comprehensive modeling of NAND flash memory reliability: Endurance and data retention

Cited by 33 publications

References 7 publications

Experimental Investigation of Threshold Voltage Temperature Effect During Cross-Temperature Write–Read Operations in 3-D NAND Flash

Experimental Investigation of Threshold Voltage Temperature Effect During Cross-Temperature Write–Read Operations in 3-D NAND Flash

Advanced error-prediction LDPC with temperature compensation for highly reliable SSDs

Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory

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