Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory

Shen, Xinshuai; Xia, Zeyang; Yang, Tao; Liu, Lei; Dong, Jinwen; Zhou, Wenxi; Li, Chunlong; Huo, Zongliang

doi:10.1109/jeds.2020.3024235

Cited by 11 publications

(8 citation statements)

References 18 publications

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“…In addition to solving Equation (5), it requires computing an additional smooth distortion u δ to fulfill the condition of mechanical equilibrium, i.e., ∇ • σ = 0. The stress field σ can be decomposed into two parts σ ψ and σ δ .…”

Section: Deformation and Boundary Conditionmentioning

confidence: 99%

“…Along with parallel development in size miniaturization, manufacturing processes of TSVs have been improved to accommodate the scaling of semiconductors and satisfy the demands for high performances at the same time. Novel processes of 3D packaging technologies utilizing TSVs have been invented, such as CoWoS from TSMC [3], Foveros from Intel [4], and X-stacking from Changjiang Storage [5].…”

Section: Introductionmentioning

confidence: 99%

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Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model

et al. 2022

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As thermal management in 3DIC integration becomes increasingly important in advanced semiconductor node processes, novel experimental and modeling approaches are in great demand to reveal the critical material issues involving multiscale microstructures that govern the behavior of through-silicon-via (TSV) protrusion. Here, a coarse-grained phase-field crystal model properly coupled with mechanics through the atomic density field is used to simulate the formation of polycrystalline structures and protrusion of nano-TSVs from the atomic scale. TSVs with different grain structures are directly loaded, and protrusion/intrusion profiles are obtained along with displacement, stress, and strain fields. Thermodynamic driving forces from external loadings and the mismatch of Young’s modulus between adjoining grains as well as detailed displacement and strain distributions are ascribed to control the complex deformation in TSVs. TSVs with sizes up to around 30 nm and an aspect ratio of 4 are successfully investigated, and a further increase in the size and aspect ratio to cover the micrometer range is feasible, which lays down a solid basis toward a multiscale material database for simulation inputs to the design of TSV-based 3DIC integration and relevant electronic design automation (EDA) tools.

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Section: Deformation and Boundary Conditionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model

et al. 2022

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“…A simplified cross-sectional view of a 3D NAND Flash test chip is shown in Figure 1. Two stacking wafers are connected together by millions of bonding interface vias (BIVs) [17,18]. As shown in the figure, the ESD pad on the backside of the upper wafer is connected to the ESD clamp circuit on the lower wafer through BIVs in between the two wafers [21][22][23][24].…”

Section: Esd Clamp Device Structurementioning

confidence: 99%

“…Nowadays, NAND Flash memory is widely used in mass storage applications. Threedimensional NAND Flash memory with 3D stacked IC (SIC) [17,18] is the most viable solution for high-capacity storage and low-bit-cost non-volatile memory [19,20]. During the contact-type usage, the pins of packaged die may be exposed to ESD sources such as human fingers; hence, ESD immunity is required for NAND Flash memory.…”

Section: Introductionmentioning

confidence: 99%

Analysis of HBM Failure in 3D NAND Flash Memory

Song

Li²,

Wang³

et al. 2022

Electronics

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Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

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“…A complete NAND flash memory chip is mainly composed of flash memory particles and CMOS peripheral circuits. At present, the construction of CMOS peripheral circuits mainly includes the following three ways: CMOS next Array (CnA) [1], [2], CMOS under array (CuA) [3], [4] and Xtacking [5], [6]. But no matter which way it is, the NAND flash array and peripheral circuits need to be prepared on different layers and by different processes.…”

Section: Introductionmentioning

confidence: 99%

Transparent Multi-Level NAND Flash Memory and Circuits Based on ZnO Thin Film Transistor

Zhang

Zhao

Chong

et al. 2023

IEEE Electron Device Lett.

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Hydrogen Source and Diffusion Path for Poly-Si Channel Passivation in Xtacking 3D NAND Flash Memory

Cited by 11 publications

References 18 publications

Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model

Simulation of TSV Protrusion in 3DIC Integration by Directly Loading on Coarse-Grained Phase-Field Crystal Model

Analysis of HBM Failure in 3D NAND Flash Memory

Transparent Multi-Level NAND Flash Memory and Circuits Based on ZnO Thin Film Transistor

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