Experimental Investigation of Threshold Voltage Temperature Effect During Cross-Temperature Write–Read Operations in 3-D NAND Flash

Abstract

Reading data at a temperature which different from writing can cause a large number of failed bits in 3D NAND Flash memory. In this work, the threshold voltage(Vth) temperature effect of 3D NAND flash memory cell was investigated and a method was proposed to optimize its temperature coefficient(Tco). The results suggested that the Tco of low temperature programmed high temperature read is larger than high temperature programmed low temperature read and this difference is about 2-3mv/℃, which makes against the temperature compensation of reading voltage and lead to irreparable data errors even there is error correction codes. Furthermore, the critical factor of this difference was demonstrated that is the charge loss during low temperature programmed high temperature read and the Vth shift caused by charge loss is up to 30 percent. Based on this, we proposed to optimize the Tco consistency by shortening the interval time of erase to program in endurance cycling stage and confirmed that this method is effective by experiment. As the time interval becomes smaller, the difference of the Tco decreases as well, which have great reference signification for improving the reliability of 3D NAND flash memory.

Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory

“…The ΔVT,CL has a negative value up to 4 h. Figure 6b shows the absolute values of the decomposed ΔVT,4h at TPGM = 75 °C and 120 °C. The ΔVT,CL diminishes at the elevated TPGM due to the fact that the higher TPGM results in more significant charge loss within the initial 30 s, corresponding to the range of shortterm retention [26,31,32]. The ΔVT,GB increases at the elevated TPGM due to the decrease in ΦB of the GB at higher temperatures.…”

“…The relevant temperature coefficient in the compensation circuit differs among individual cells [24]. Even in the same cell, this coefficient varies depending on the temperature conditions: a high temperature program and low temperature read (HPLR) condition or a low temperature program and high temperature read (LPHR) condition [25,26]. Therefore, more detailed analyses at the cell level are needed to understand the cross-temperature phenomena and effectively reduce the fail bits in 3-D NAND.…”

A polynomial based valley search algorithm for 3D NAND flash memory

“…After the program operation, the threshold voltage of the cell is divided to multiple states. Reliability problems will lead to changes in threshold voltage distribution [20,21,22,23,24], such as temperature and cycling, but the distribution of a single state always approximately obeys the Gaussian distribution as studied in [25,26,27,28,29,30]. However, the distribution of different program states is not exactly the same, especially the highest state.…”

Temperature Impacts on Endurance and Read Disturbs in Charge-Trap 3D NAND Flash Memories

“…Zambelli et al studied cross-temperature effects in 2D and 3D NAND flash memories and found that there was a large number of fail-bits when the memory was read at a temperature different from that exercised during the program [ 13 ]. Wu et al found that cell values had various offset and velocities for different temperate operations, and it can be reduced by shortening the interval time from erase to program during cross-temperature write–read stages [ 14 ]. Kong et al studied the read disturbs in a 3D CT NAND flash memory, and observed that read disturbs were strongly correlated to retention time and temperatures, and proposed the schemes of precharge-the-storage-layer (PCSL) and thermally-stabilize-the-storage-layer (TSSL) to suppress read disturbs [ 8 ].…”