Complete transient simulation of flash EEPROM devices

Keeney, S.; Bez, R.; Cantarelli, D.; Piccinini, F.; Mathewson, A.; Ravazzi, L.; Lombardi, C.

doi:10.1109/16.168729

Cited by 31 publications

(10 citation statements)

References 19 publications

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“…Threshold voltage depends on oxide thickness (Fig. 18) [48], as explained in Section III-B. From the same figure, one can infer that after electrical erase, cells with the same oxide thickness but different initial values of threshold voltage will reach the same threshold voltage at the end of the erase operation.…”

Section: ) Programmentioning

confidence: 76%

“…At this point, we can define an intrinsic threshold. The electric field in the tunnel oxide close to the drain reverses and electron injection into the FG is much less favorable [47]. Intrinsic threshold voltage shift roughly does not depend on the channel length of the cell (Fig.…”

Section: ) Programmentioning

confidence: 96%

“…The threshold shift depends on source voltage (Fig. 17) and, as a rule of thumb, a one-order-of-magnitude increase in erasing time occurs for each volt reduction in source voltage [47]. Threshold voltage depends on oxide thickness (Fig.…”

Section: ) Programmentioning

confidence: 99%

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Flash memory cells-an overview

et al. 1997

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Section: ) Programmentioning

confidence: 76%

Section: ) Programmentioning

confidence: 96%

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Flash memory cells-an overview

et al. 1997

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“…As a consequence, different non-Maxwellian expressions for the energy distribution function have been proposed, usually derived from Monte Carlo results by a fitting procedure [36], or obtained directly from the Boltzmann equation under simplifying assumptions [37). Furthermore, gate-current models have been incorporated into hydrodynamic simulators [38,39], which are less demanding in terms of computation time than the Monte Carlo ones and are consequently commonly used in the technology development.…”

Section: Physical Modelmentioning

confidence: 99%

Hydrodynamic simulation of semiconductor devices

Rudan

Lorenzini

Brunetti

1998

Theory of Transport Properties of Semiconductor Nanostructures

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INTRODUCTIONRecently the hydrodynamic model has become popular in the field of analysis and simulation of semiconductor devices*. The model has the merit of providing, along with the concentration and current density of the carriers, also their average energy and average energy flux. At the same time, its equations basically retain the same structure of the simpler drift-diffusion model; because of this, it has been possible to incorporate the hydrodynamic equations into existing deviceanalysis codes, thus exploiting a number of robust solution schemes already available there.The hydrodynamic model is derived by applying the moment technique to the Boltzmann transport equation (BTE) and truncating the series of moments at a suitable order. This yields a number of partial differential equations in the r, t space, specifically, the continuity equations for the carrier number, momentum, average energy and average energy flux. In this procedure, due to the integration over the wave vector space and to the series truncation, some of the information originally carried by the distribution function is lost. However, the information provided by the continuity equations indicated above is in most cases sufficient to describe the electrical behaviour of realistic semiconductor devices.It is worth noting that the term hydrodynamic model is not always given exactly the same meaning in the existing literature. What is meant here by this term is a model derived through the following steps: * Part of this work was carried out within ADEQUAT (JESSI BTl I, ESPRIT 8002) and DESSIS (ESPRIT 6075). E. Schöll (ed.), Theory of Transport Properties of Semiconductor Nanostructures

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“…8 V/cm [18] to 1.9x10 8 V/cm [19]. In either case, one can fit curves of the form aV n G for particular values of TOX to the…”

Section: Gate Leakage Powermentioning

confidence: 99%

Why Area Might Reduce Power in Nanoscale CMOS

Beckett

Goldstein

2005 IEEE International Symposium on Circuits and Systems

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Abstract-In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reduction in V DD which results in a reduction in power. Under a scaling regime which allows threshold voltage to increase as V DD decreases we find that dynamic and subthreshold power loss in CMOS exhibit a dependence on area proportional to A (σ−3)/σ while gate leakage power ∝ A (σ−6)/σ and short circuit power ∝ A (σ−8)/σ . Thus, with the large number of devices at our disposal we can exploit techniques such as spatial computing-tailoring the program directly to the hardware-to overcome the negative effects of scaling. The value of σ describes the effectiveness of the technique for a particular circuit and/or algorithm-for circuits that exhibit a value of σ ≤3, power will be a constant or reducing function of area. We briefly speculate on how σ might be influenced by a move to nanoscale technology.

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Complete transient simulation of flash EEPROM devices

Cited by 31 publications

References 19 publications

Flash memory cells-an overview

Flash memory cells-an overview

Hydrodynamic simulation of semiconductor devices

Why Area Might Reduce Power in Nanoscale CMOS

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