Why Area Might Reduce Power in Nanoscale CMOS

Abstract

Abstract-In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reduction in V DD which results in a reduction in power. Under a scaling regime which allows threshold voltage to increase as V DD decreases we find that dynamic and subthreshold power loss in CMOS exhibit a dependence on area proportional to A (σ−3)/σ while gate leakage power ∝ A (σ−6)/σ and short circuit power ∝ A (σ−8)/σ . Thus, with the large number of devices at our disposal we can exploit techniques such as spatial computing-tailoring the program directly to the hardware-to overcome the negative effects of scaling. The value of σ describes the effectiveness of the technique for a particular circuit and/or algorithm-for circuits that exhibit a value of σ ≤3, power will be a constant or reducing function of area. We briefly speculate on how σ might be influenced by a move to nanoscale technology.

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