Comparison of Delay Tests on Silicon

Qiu, Wangqi; Walker, D.M.H.; Simpson, Nelson; Reddy, D V Rama Koti; Moore, Andrew C.

doi:10.1109/test.2006.297624

Cited by 4 publications

(2 citation statements)

References 32 publications

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“…A KLPG-1 test set, consisting of the robust longest rising and falling path through each line, topped off with non-robust KLPG patterns, topped off with long transition fault patterns, achieves the same transition fault coverage as a transition fault test set, but with higher quality, since it targets smaller delay defects [9] [10]. The drawback of a KLPG-1 test set has been increased pattern count.…”

Section: Pattern Count Comparisonmentioning

confidence: 99%

“…In [7], an efficient automatic test pattern generation (ATPG) algorithm was developed to test the K Longest Paths Per Gate (KLPG) in a combinational circuit and extended to sequential circuits in [8]. A fault coverage metric was developed to show the theoretical high quality of KLPG [ 9 ] and the benefits demonstrated on silicon in [10]. The primary barrier to the use of KLPG patterns has been the high pattern count.…”

Section: Introductionmentioning

confidence: 99%

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Dynamic Compaction for High Quality Delay Test

Wang

Walker

2008

26th IEEE VLSI Test Symposium (Vts 2008)

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Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scanbased sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality. The path delay fault model [ 1 ] is used to detect distributed and small delay defects in integrated circuits. The challenge of the path delay fault model is that the number of paths is exponential in the circuit size. One strategy is to target a subset of paths which contains at least one of the longest testable paths passing through each line or gate [2 ][ 3 ][ 4 ][ 5 ][ 6 ][ 7 ][ 8 ]. In [7], an efficient automatic test pattern generation (ATPG) algorithm was developed to test the K Longest Paths Per Gate (KLPG) in a combinational circuit and extended to sequential circuits in [8]. A fault coverage metric was developed to show the theoretical high quality of KLPG [ 9 ] and the benefits demonstrated on silicon in [10]. The primary barrier to the use of KLPG patterns has been the high pattern count. The existing CodGen ATPG tool [7][8] uses greedy, forwardorder static compaction. This paper investigates improved compaction algorithms. Many compaction algorithms have been proposed in the literature for test compaction in combinational and fully-scanned sequential circuits. After test generation, static compaction [11][12][13][14] is performed to reduce pattern count without reducing fault coverage. Dynamic compaction [11] is performed during test generation, and can achieve greater reduction in pattern count. Many dynamic compaction methods [ 15][ 16 ][ 17 ][ 18 ] aim at maximizing the number of stuck-at faults detected by a test pattern. The classic approach is to generate a pattern for one fault, and then use heuristics to modify the unspecified bits, and drop other detected faults in the fault list via fault simulation. This approach does not work well for path delay test due to the low fortuitous detection rate. Several compaction techniques targeting path delay faults have been proposed [19][20] [21]. In [19], maximal compatible path delay fault sets are first derived based on a six-valued algebra and then a test is generated for faults in each of these sets. The memory requirements depend on the number of paths and the number of lines in a path. The approaches in [20][21] try to simultaneously test paths with crossing points so as to fortuitously detect many faults which may not be included in the target fault list. This is similar to fortuitou...

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Section: Pattern Count Comparisonmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Dynamic Compaction for High Quality Delay Test

Wang

Walker

2008

26th IEEE VLSI Test Symposium (Vts 2008)

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Coping with Physical Failures, Soft Errors, and Reliability Issues

Wang

Nourani

Mak

2008

System-on-Chip Test Architectures

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Modeling Test Escape Rate as a Function of Multiple Coverages

Butler

Carulli

Saxena

2008

2008 IEEE International Test Conference

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The Williams and Brown Model has long been the gold standard for estimating test escape rate as a function of yield and fault coverage. However, today's test programs have a number of differing test types, often with overlapping failing unit detections. This paper details the development of a method which permits test escape rate predictions based on product yield and multiple overlapping test coverages.

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Comparison of Delay Tests on Silicon

Cited by 4 publications

References 32 publications

Dynamic Compaction for High Quality Delay Test

Dynamic Compaction for High Quality Delay Test

Coping with Physical Failures, Soft Errors, and Reliability Issues

Modeling Test Escape Rate as a Function of Multiple Coverages

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