Modeling Test Escape Rate as a Function of Multiple Coverages

Butler, K.M.; Carulli, John M.; Saxena, J.

doi:10.1109/test.2008.4700605

Cited by 8 publications

(1 citation statement)

References 38 publications

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“…For several years now, test is being expanded as a value-added endeavor [1,19,20]. In particular, the diagnosis of test data for improving yield is a topic of great interest [2][3][4][5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

Controlling DPPM through Volume Diagnosis

Lin

Tam

et al. 2009

2009 27th IEEE VLSI Test Symposium

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We propose to achieve and maintain ultra-high quality of digital circuits on a per-design basis by (i) monitoring the type of failures that occur through volume diagnosis, and (ii) changing the test patterns to match the current failure population characteristics. Opposed to the current approach that assumes sufficient quality levels are maintained using the tests developed during the time of design, the methodology described here presupposes that fallout characteristics can change over time but with a time constant that is sufficiently slow, thereby allowing test content to be altered so as to maximize coverage of the failure types actually occurring. Even if this assumption proves to be false, the test content can be tuned to match the characteristics of the fallout population if the fallout characteristics are unchanging. Under either scenario, it should be then possible to minimize DPPM for a given constraint on test costs, or alternatively ensure that DPPM does not exceed some pre-determined threshold. Our approach does not have to cope with situations where fallout characteristics change rapidly (e.g. excursion), since there are existing methods to deal with them. Our methodology uses a diagnosis technique that can extract defect activation conditions, a new model for estimating DPPM, and an efficient test selection method for reducing DPPM based on volume diagnosis results. Circuit-level simulation involving various types of defects shows that DPPM could be reduced by 30% using our methodology. In addition, experiments on a real silicon chip failures show that DPPM can be significantly reduced, without additional test execution cost, by altering the content (but not the size) of the applied test set.

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