Dynamic Compaction for High Quality Delay Test

Abstract

Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scanbased sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality. The path delay fault model [ 1 ] is used to detect distributed and small delay defects in integrated circuits. The challenge of the path delay fault model is that the number of paths is exponential in the circuit size. One strategy is to target a subset of paths which contains at least one of the longest testable paths passing through each line or gate [2 ][ 3 ][ 4 ][ 5 ][ 6 ][ 7 ][ 8 ]. In [7], an efficient automatic test pattern generation (ATPG) algorithm was developed to test the K Longest Paths Per Gate (KLPG) in a combinational circuit and extended to sequential circuits in [8]. A fault coverage metric was developed to show the theoretical high quality of KLPG [ 9 ] and the benefits demonstrated on silicon in [10]. The primary barrier to the use of KLPG patterns has been the high pattern count. The existing CodGen ATPG tool [7][8] uses greedy, forwardorder static compaction. This paper investigates improved compaction algorithms. Many compaction algorithms have been proposed in the literature for test compaction in combinational and fully-scanned sequential circuits. After test generation, static compaction [11][12][13][14] is performed to reduce pattern count without reducing fault coverage. Dynamic compaction [11] is performed during test generation, and can achieve greater reduction in pattern count. Many dynamic compaction methods [ 15][ 16 ][ 17 ][ 18 ] aim at maximizing the number of stuck-at faults detected by a test pattern. The classic approach is to generate a pattern for one fault, and then use heuristics to modify the unspecified bits, and drop other detected faults in the fault list via fault simulation. This approach does not work well for path delay test due to the low fortuitous detection rate. Several compaction techniques targeting path delay faults have been proposed [19][20] [21]. In [19], maximal compatible path delay fault sets are first derived based on a six-valued algebra and then a test is generated for faults in each of these sets. The memory requirements depend on the number of paths and the number of lines in a path. The approaches in [20][21] try to simultaneously test paths with crossing points so as to fortuitously detect many faults which may not be included in the target fault list. This is similar to fortuitou...

Power supply noise control in pseudo functional test

“…Test compaction [10,23] is used to reduce pattern count and minimize test time. Compacted patterns typically have higher care-bit density, which reduces the search space for PSN control.…”

High-quality pattern selection for screening small-delay defects considering process variations and crosstalk

“…It selects all logically sensitizable long paths using worst-case statistical timing information and obtains the true timing information of the selected paths. In [15], the authors proposed a dynamic pattern compaction method for path delay patterns. The 2K longest paths, K paths having the rising transition and K paths having the falling transition, through each fault site were reported for path delay pattern generation.…”

A scalable method for the generation of small test sets

“…The work in [15] uses necessary assignments (NA) for sensitizing selected paths in order to create compact test sets to detect transition faults through longest testable paths. A NA set of faults, is a subset of faults such that necessary assignments of any pair of paths in the set do not conflict.…”

“…A NA set of faults, is a subset of faults such that necessary assignments of any pair of paths in the set do not conflict. In [15], the collection of NAs for all paths in a set are called set assignments (CA). Next, tests to satisfy all necessary assignments of CA are derived.…”

“…So, the problem of creating a test for these faults is reduced to justifying the necessary assignments for sensitizing the faults. In [15] it is pointed out that once a set C is formed, it is very rare that the necessary assignments in the corresponding CA cannot be simultaneously justified.…”