A scalable method for the generation of small test sets

Abstract

This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compatible faults based on necessary assignments. It guides the justification and propagation decisions to create patterns that will accommodate most targeted faults. The technique presented achieves close to minimal test pattern sets for ISCAS circuits. For industrial circuits it achieves much smaller test pattern sets than other methods in designs sensitive to decision order used in ATPG.

Improved SAT-based ATPG: More constraints, better compaction

“…The run time has been constantly higher than, for instance, the approach in [11] or Atalanta (with the exception b15). However, it can also be seen that for larger circuits, i.e.…”

“…Column MinPat shows the best known results of generated test sets in the literature, i.e. taken from [9], [11], [13], and column [11] presents the test set sizes of the most recently proposed structural ATPG approach. These approaches use post-processing techniques such as redundant vector elimination, multiple target test generation, and grouping techniques.…”

“…Several structural techniques have been introduced in order to achieve high compaction. These techniques range from static compaction and ordering techniques [3]- [6] to fault grouping and heuristics [5], [7]- [11] as well as to post-processing techniques [12], [13].…”

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

“…By this, tests for the majority of faults can be generated very fast. Dynamic compaction techniques [2][3][4][5] achieve a high compaction. However, this kind of algorithms has problems to cope with the increasing amount of hard-to-detect faults.…”

Design for test methods to reduce test set size

“…Methods to reduce test pattern counts can be classified into two classes. The first one is software or algorithm based that typically use heuristics to improve ATPG procedures to achieve lower test pattern counts [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38]. Typically, these methods try to maximize the number of faults detected by a generated test.…”