Improved SAT-based ATPG: More constraints, better compaction

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

et al. 2014

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Abstract-It is well-known that in principle automatic test pattern generation (ATPG) can be solved by transforming the circuit and the fault considered into a Boolean satisfiability (SAT) instance and then calling a so-called SAT solver to compute a test. More recently, the potential of SAT-based ATPG has been significantly extended. In this paper, we first provide introductory knowledge on SAT-based ATPG and then report on latest developments enabling applications far beyond classical ATPG.

Section: B Local Fault Detectionmentioning

confidence: 99%

Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization

Becker

Drechsler

2014 9th IEEE International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

et al. 2014

Self Cite

“…Recently, SAT-based and optimization methods based on efficient SAT solving engines attracted attention in the field of test generation [19]- [23], i.e. by reducing aborts, maximizing fault detection and power-droop conditions.…”

Section: A Related Prior Workmentioning

confidence: 99%

Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill

2013 22nd Asian Test Symposium

2013

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Abstract-Excessive test power consumption is one of the obstacles which the chip industry currently faces. Peak capture power reduction typically leads to high pattern counts which increase test costs. This paper proposes a new methodology to reduce peak capture power during at-speed scan testing. In this method, a novel X-filling technique Opt-Justification-fill which uses optimization techniques to compute promising Xbits for low-power filling is proposed. This method is tightly integrated into a dynamic compaction flow to create silent test cubes with high compaction ability. By this, X-filling for fault detection and reducing switching activity is balanced. The proposed methodology can be applied during initial compact test set generation as well as a post-ATPG stage for a previously generated test set to reduce switching activity. Experiments show a significant reduction of peak capture power. At the same time, the pattern count increases only moderately which leads to reduced test costs.

“…A recent work [20] follows a different approach. Instead of substituting specified bits by -values, the prob-lem formulation is extended by local fault detection constraints for undetected faults.…”

Section: Dynamic Test Compactionmentioning

confidence: 99%

“…In this section, we propose a new fault ordering heuristic which is applied in the SAT-based dynamic test compaction approach [20]. The proposed ordering technique leverages information extracted from the untestable identification phase.…”

Section: Fault Ordering Heuristicmentioning

confidence: 99%

“…Instead of following the classical way of targeting one fault at a time, the problem of generating a compact test set is considered as a whole. Instead of targeting faults explicitly, the approach presented in [20] encodes local fault detection constraints into the SAT instance and uses a Pseudo-Boolean Optimization (PBO) procedure to generate a test which is likely to detect more faults. By this, a highly compacted test set can be generated.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

An effective fault ordering heuristic for SAT-based dynamic test compaction techniques

It - Information Technology

Drechsler²

2014

Self Cite

Each chip is subjected to a post-production test after fabrication. A set of test patterns is applied to filter out defective devices. The size of this test set is an important issue. Generally, large test sets increase the test costs. Therefore, test compaction techniques are applied to obtain a compact test set. The effectiveness of these technique is significantly influenced by fault ordering. This paper describes how information about hard-to-detect faults can be extracted from an untestable identification phase and be used to develop a fault ordering technique which is able to reduce the pattern counts of highly compacted test sets generated by a SAT-based dynamic test compaction approach.