Comparison between CMOS full adder and PTL full adder

Amitha, M.; Deepa,

doi:10.1088/1757-899x/1065/1/012047

Cited by 4 publications

(2 citation statements)

References 7 publications

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“…Moreover, it used NMOS and PMOS instead of two pass gates to perform the majority logic. It has been widely discussed because of its simple circuitry and threshold loss issue [29]. In 1999, a 14-transistor full adder was proposed [30], as shown in Figure 12.…”

Section: Existing Full Addersmentioning

confidence: 99%

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Yin

Pan

et al. 2023

Electronics

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With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.

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Section: Existing Full Addersmentioning

confidence: 99%

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Yin

Pan

et al. 2023

Electronics

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“…The Boolean Expression also represents the topology in which the digital gates are combined to create the final output. It is important to note in the above circuit for the full Adder that the inputs A, B and C are applied at the inputs of the AND Gate and the output of the AND Gates are then applied at input of the OR Gate to generate the final output [11].…”

Section: Introductionmentioning

confidence: 99%

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Rajitha

2024

IJRASET

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In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

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Efficient Approaches to Design Full Adder Using Domino Logic Technique

G.Tejaswini¹

2023

IJETMS

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Static CMOS and Domino CMOS Circuits are significantly used in high performance VLSI system. Designing a circuit with low power, high speed performance is one of the challenging aspects. In modern VLSI systems area efficient devices are utmost popular because most of the devices are becoming portable. This paper proposes One- bit full adder circuit is designed using CMOS based on mirror logic and Domino CMOS also designed based on same logic with LTSPICE at 180nm technology with 1.8V supply. This method provides better power and delay.

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Comparison between CMOS full adder and PTL full adder

Cited by 4 publications

References 7 publications

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Efficient Approaches to Design Full Adder Using Domino Logic Technique

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