Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Yin, Ningyuan; Pan, Wubin; Yu, Yun Seop; Tang, Chengcheng; Yu, Zhiyi

doi:10.3390/electronics12153209

Cited by 5 publications

(2 citation statements)

References 33 publications

(36 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus variable Carry-Out represents that output of the Full Adder which is carried out on the addition of the two or three binary digits. Thus the Carry-Out (C-Out) bit is 1 when any two of the inputs are 1 or all of the inputs of the full adder are 1 [8]. Boolean Expression of the digital combinational circuit represents the input and output relationship of the circuit [9].…”

Section: Introductionmentioning

confidence: 99%

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Rajitha

2024

IJRASET

View full text Add to dashboard Cite

In electronic industry the level of integration is an important aspect as it makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, Area occupied and Propagation delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Many binary adders are formed using full adders. Hence, if any enhancements have to be made to improve the performance, it can be made at the root level i.e., adders circuits itself. This in turn helps in bettering the performance of the electronics circuits which follow adder circuits. The low power VLSI design is of great importance due to portable electronic products. Full adder is a type of adder circuit that adds three inputs and gives two outputs. Out of three, two will be the present inputs and the third input will be the carry from the previous stage. ‘A’ and ‘B’ are the actual inputs, ‘C’ is the carry from the previous operation. SUM and CARRY OUT are the two outputs. In this work, Design and Implementation of full adder using conventional CMOS design and Pass Transistor Logic based Full adder circuits are carried out. At last comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Cadence Virtuoso Tool is used in design and simulation conventional CMOS design and Pass Transistor Logic based Full adder circuits. The entire work is simulated in 180nm CMOS technology.

show abstract

Section: Introductionmentioning

confidence: 99%

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Rajitha

2024

IJRASET

View full text Add to dashboard Cite

show abstract

“…As discussed in [14], it is essential to acknowledge that PTL circuits may suffer from insufficient driving capability and threshold voltage loss due to structural reasons. Moreover, the cascaded PTL-based circuits might incur a cascade R-C chain, resulting in a decrease in output swing and an exponential increase in delay [15]. At present, the solutions to these problems are rarely mentioned in existing literature, especially when applied to complex circuits.…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

Self Cite

View full text Add to dashboard Cite

The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

show abstract

IoT-driven optimization of a NxN enhanced pipeline multiplier

Mohammad,

Al-Sheikh

2024

Computers and Electrical Engineering

View full text Add to dashboard Cite

Low-Power Pass-Transistor Logic-Based Full Adder and 8-Bit Multiplier

Cited by 5 publications

References 33 publications

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Implementation and Analysis of CMOS and Pass Transistor Logic Based Full Adder Circuits

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

IoT-driven optimization of a NxN enhanced pipeline multiplier

Contact Info

Product

Resources

About