In this report, we present a vertical memristor based on a layered FePS3 two-dimensional material with the structure Ag/FePS3/Au, where FePS3 is a single-crystalline layer with a thickness of ∼151 nm. By operating a device with a pulse voltage of 0.1 V dual modes of resistive switching with both analog and digital features are implemented in a single device. One mode lies between the OFF and ON states and another lies in the ON state. The device shows nonvolatility. Short-term plasticity and long-term potentiation are observed. Therefore, the FePS3 memristor is suitable for application in flexible and complex neuromorphic systems.
With the rapid development of information technology, the demand for high-speed and low-power technology for digital signal processing is increasing. Full adders and multipliers are the basic components of signal processing technology. Pass-transistor logic is a promising method for implementing full adder and multiplier circuits due to the low count of transistors and low-power characteristics. In this paper, we present a novel full adder based on pass transistors. The proposed full adder consists of 18 transistors. The post-layout simulation shows a 13.78% of power reduction compared to conventional CMOS full adders. Moreover, we propose an 8-bit signed multiplier based on the proposed full adder. The post-layout simulation shows an 8% power reduction compared to the multiplier produced by the Design Compiler synthesis tool. Compared to the existing work with a similar process, our work achieved only 19.02% of the power-delay product and 3.5% of the area-power product.
Traditional von Neumann architecture bottlenecks such as the "memory wall" limit artificial intelligence (AI) development, and inmemory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.
In-memory computing (IMC) quantized neural network (QNN) accelerators are extensively used to improve energy-efficiency. However, ternary neural network (TNN) accelerators with bitwise operations in nonvolatile memory are lacked. In addition, specific accelerators are generally used for a single algorithm with limited applications. In this report, a multiply-and-accumulate (MAC) circuit based on ternary spin-torque transfer magnetic random access memory (STT-MRAM) is proposed, which allows writing, reading, and multiplying operations in memory and accumulations near memory. The design is a promising scheme to implement hybrid binary and ternary neural network accelerators.
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