High speed, Low Resource and Non-volatile MTJ-CMOS Hybrid Logical Circuits

Chen, Jianjun; Yin, Ningyuan; Yu, Zhiyi

doi:10.1109/icsict.2018.8564892

Cited by 3 publications

(3 citation statements)

References 7 publications

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“…One critical issue in these hybrid CMOS/MTJ logic circuits is to correctly sense the information stored in the MTJ [19][20][21][22][23]. So far, various DSAs have been proposed, in which two MTJs with opposite resistance states are employed to represent one bit.…”

Section: Introductionmentioning

confidence: 99%

“…By using the positive feedback of two PMOS transistors, the proposed DSA is envisioned to obtain a large sensing margin, thereby achieving high sensing reliability. One critical issue in these hybrid CMOS/MTJ logic circuits is to correctly sense the information stored in the MTJ [19][20][21][22][23]. So far, various DSAs have been proposed, in which two MTJs with opposite resistance states are employed to represent one bit.…”

Section: Introductionmentioning

confidence: 99%

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A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Wang

Yang²,

Han³

et al. 2023

Electronics

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Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR ≤ 150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with a TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Wang

Yang²,

Han³

et al. 2023

Electronics

View full text Add to dashboard Cite

show abstract

“…One critical issue in these hybrid CMOS/MTJ logic circuits is to correctly sense the information stored in the MTJ [11][12][13][14]. So far, various differential sensing amplifiers (DSAs) have been proposed, in which two MTJs with opposite resistance state are employed to represent one bit.…”

Section: Introductionmentioning

confidence: 99%

A Reliability-Enhanced Differential Sensing Amplifier for Hybrid CMOS/MTJ Logic Circuits

Wang¹,

Wang²,

Wang³

et al. 2022

Preprint

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Recently, hybrid logic circuits based on magnetic tunnel junctions (MTJs) have been widely investigated to realize zero standby power. However, such hybrid CMOS/MTJ logic circuits suffer from a severe sensing reliability due to the limited tunnel magnetoresistance ratio (TMR≤150%) of the MTJ and the large process variation in the deep sub-micrometer technology node. In this paper, a novel differential sensing amplifier (DSA) is proposed, in which two PMOS transistors are added to connect the discharging branches and evaluation branches. Owing to the positive feedback realized by these two added PMOS transistors, it can achieve a large sensing margin. By using an industrial CMOS 40 nm design kit and a physics-based MTJ compact model, hybrid CMOS/MTJ simulations have been performed to demonstrate its functionality and evaluate its performance. Simulation results show that it can achieve a smaller sensing error rate of 9% in comparison with the previously proposed DSAs with the TMR ratio of 100% and process variation of 10%, while maintaining almost the same sensing delay of 74.5 ps and sensing energy of 1.92 fJ/bit.

show abstract