Compact core model for Symmetric Double-Gate Junctionless Transistors

Cerdeira, A.; Avila, Fernando; Iñı́guez, Benjamı́n; Souza, Michelly de; Pavanello, Marcelo Antonio; Estrada, M.

doi:10.1016/j.sse.2014.02.011

Cited by 23 publications

(8 citation statements)

References 12 publications

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“…Many models were proposed, and the difference among them depends on the approximations that are involved in the derivation and the considered effects. For instance, many models do not consider short channel and quantum effects [53,55,58,66], while others are only valid for certain doping concentrations and device layer thickness ranges [59,61]. Quantum effects are critically important, because they can affect the threshold voltage [74].…”

Section: Double Gatementioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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Recent advances in semiconductor technology provide us with the resources to explore alternative methods for fabricating transistors with the goal of further reducing their sizes to increase transistor density and enhance performance. Conventional transistors use semiconductor junctions; they are formed by doping atoms on the silicon substrate that makes p-type and n-type regions. Decreasing the size of such transistors means that the junctions will get closer, which becomes very challenging when the size is reduced to the lower end of the nanometer scale due to the requirement of extremely high gradients in doping concentration. One of the most promising solutions to overcome this issue is realizing junctionless transistors. The first junctionless device was fabricated in 2010 and, since then, many other transistors of this kind (such as FinFET, Gate-All-Around, Thin Film) have been proposed and investigated. All of these semiconductor devices are characterized by junctionless structures, but they differ from each other when considering the influence of technological parameters on their performance. The aim of this review paper is to provide a simple but complete analysis of junctionless transistors, which have been proposed in the last decade. In this work, junctionless transistors are classified based on their geometrical structures, analytical model, and electrical characteristics. Finally, we used figure of merits, such as I o n / I o f f , D I B L , and S S , to highlight the advantages and disadvantages of each junctionless transistor category.

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Section: Double Gatementioning

confidence: 99%

Junctionless Transistors: State-of-the-Art

2020

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“…Although there are numerous compact drain current models reported for JL transistors for long-channel [3][4][5][6][7][8][9][10] and short channel devices [11][12][13][14][15][16], the literature reveals only a handful of intrinsic capacitance models. For double-gate junctionless transistors, a charge based analytical model for long-channel devices has been developed in [17].…”

Section: Introductionmentioning

confidence: 99%

Continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs

Oproglidis

Tsormpatzoglou

Tassis

et al. 2021

Solid-State Electronics

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“…Moreover, by reducing the contacts' separating region, it is possible to get higher ON-OFF switching performance. Despite that several experimental and numerical studies published recently have shown the superior fabrication process properties provided by the junctionless device in comparison with the conventional one [4][5][6], the junctionless structure is more vulnerable to the impact of the source/drain parasitic resistance compared to an inversion mode structure [7,8]. The high series resistance associated to the source and drain regions can arise as a serious problem when dealing with uniformly doped channel, which leads to the degradation of the device performance.…”

Section: Introductionmentioning

confidence: 99%