Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs

Li, Xueqing; Wei, Qi; Yang, Huazhong

doi:10.1109/icecs.2011.6122252

Cited by 8 publications

(7 citation statements)

References 8 publications

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“…For high-speed DACs, the current source mismatches [1], [2], [8]- [10], code-dependent load variations [3]- [5], [11] and code-dependent switching glitches [2]- [4], [7] are the main issues that limit the SFDR. At higher frequencies, the finite output impedance due to parasitics worsens the code-dependent load variation and deteriorates the SFDR.…”

Section: Introductionmentioning

confidence: 99%

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Liu

Wei

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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A 14-bit 1.0-GS/s current-steering digital-to-analog converter (DAC) was designed in a 65-nm CMOS process. For such current-steering DACs with a high sampling rate, the codedependent load variations and switching glitches are a main bottleneck which limits the spurious-free dynamic range (SFDR). Dynamic element matching (DEM) has been an effective solution to randomize these glitches for a higher SFDR and also to reduce the matching requirement of the current cells for an areaefficient design which also improves the SFDR with reduced parasitic capacitance. An effective method named TRI-DEMRZ is proposed in this paper, consisting of time-relaxed interleaving, DEM and return-to-zero encoding. We also apply TRI-DEMRZ in synergy with complementary switched current sources (CSCS) to design the DAC for the purpose of a small die size and enhanced SFDR performance. Post-layout simulations show >80 dB SFDR up to the Nyquist. This DAC has a mixed 1.2 V / 2.5 V power supply and an active area of 0.48 mm 2 . Keywords-Digital-to-analog converter (DAC); mismatch; Dynamic element matching (DEM); return-to-zero (RZ); spuriousfree dynamic range (SFDR)I.978-1-4799-8391-9/15/$31.00 ©2015 IEEE

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Section: Introductionmentioning

confidence: 99%

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Liu

Wei

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Larger size of current source transistor results in large parasitic capacitance at the output node which combined with large output resistance and causes lower bandwidth with higher delay. To maintain a trade-off between output impedance, bandwidth and delay, optimized transistor size is chosen [7]. Current switches made up of NMOS transistor.…”

Section: Fig 2: Schematic Design Of Current Cellmentioning

confidence: 99%

Design and analysis of 8 bit fully segmented digital to analog converter

Baranwal

Singh

2015

2015 2nd International Conference on Recent Advances in Engineering &Amp; Computational Sciences (RAECS)

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This paper presents design of an 8-bit 1.8V fully segmented digital to analog converter (DAC) using 180nm CMOS technology. DAC is an essential part of digital signal processor. Digital to analog converter is employed in processing of digital signals and providing analog output in the form of current or voltage for corresponding binary input. The differential non linearity of a DAC shows variation in output corresponding to 1LSB change at input that is accuracy of data conversion. To achieve low non linearity or more accurate data conversion a DAC is designed with unary coding or a fully segmented digital to analog converter with current steering technique. The INL and DNL achieved in this research work are 0.145LSB and 0.013LSB respectively. The power consumption is simulated as 99.67mW.

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“…12,15,16 The required signal attenuation to achieve the signal-independent ETR with different OSRs at different output frequencies is illustrated in Figure 8A where the number of current sources is 64. Besides the power consumption and timing requirement, this high operation speed also deteriorates the performance of each switching unit (the current source and the complementary switches), such as the finite output impedance, 3,24 and thus reduces the linearity. It means that, compared with a 3-GS/s Nyquist DAC with our proposed strategy, DACs with the ΔΣ-based techniques 12,15,16 require the circuits to operate at more than 15 GS/s to realize the signal-independent ETR.…”

Section: Comparisons With Similar Techniquesmentioning

confidence: 99%

“…[1][2][3][4][5][6][7][8][9][10][11] Techniques used to improve the SFDR in high-speed applications rely on more stringent clocking 1,2,12-20 (eg, half-cycle sampling) or increased area [3][4][5][6][7][8]19,[21][22][23][24] (eg, 2 interleaved sub-DACs). One key performance metric for its high-speed and wideband applications is the dynamic linearity, usually evaluated as the spurious-free dynamic range (SFDR).…”

Section: Introductionmentioning

confidence: 99%

“…When the output frequency or the sampling rate goes up, the intersymbol interference (ISI) errors during the switching transition of current sources become one of the main bottlenecks towards a higher SFDR. 1-11 Techniques used to improve the SFDR in high-speed applications rely on more stringent clocking 1,2,12-20 (eg, half-cycle sampling) or increased area [3][4][5][6][7][8]19,[21][22][23][24]…”

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confidence: 99%

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Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

Lai

Yang

2018

Circuit Theory & Apps

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This paper presents redundancy-bandwidth scalable techniques to deal with the intersymbol interference distortions for current-steering digital-to-analog converters in high-speed applications. A switching strategy that explores the use of redundant current sources is proposed to realize a signal-independent element transition rate, ie, the number of switching activities during the transition of successive sampling clock cycles. With a certain number of redundant current sources, this strategy significantly reduces the intersymbol interference distortions without oversampling operation or causing signal attenuation, which makes it appealing for high-speed applications. As analyzed in this paper, the number of required redundant current sources is scalable for different bandwidth requirement in specific applications, leading to 3 redundancy-bandwidth scalable trade-offs between the cost from redundant current sources and the high-dynamic-range bandwidth. In implementation, we propose a customdesigned decoder, named as the overlap-controlled data-weighted averaging (OC-DWA). Compared with the existing similar-purpose designs, the proposed OC-DWA decoder realizes the current sources selection with a simple barrel rotator, which is of much lower hardware complexity and energy consumption.Simulations of a digital-to-analog converter with this decoder exhibit an enhanced dynamic range over the entire Nyquist band, which verifies the redundancy-bandwidth scalability of the proposed techniques.

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Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs

Cited by 8 publications

References 8 publications

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

Design and analysis of 8 bit fully segmented digital to analog converter

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

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Code-independent output impedance: A new approach to increasing the linearity of current-steering DACs

Cited by 8 publications

References 8 publications

A 14-bit 1.0-GS/s dynamic element matching DAC with &#x003E;80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with &#x003E;80 dB SFDR up to the Nyquist

Design and analysis of 8 bit fully segmented digital to analog converter

Redundancy‐bandwidth scalable techniques for signal‐independent element transition rates in high‐speed current‐steering DACs

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A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist

A 14-bit 1.0-GS/s dynamic element matching DAC with >80 dB SFDR up to the Nyquist