Circuit‐level design technique to mitigate impact of process, voltage and temperature variations in complementary metal‐oxide semiconductor full adder cells

Dokania, Vishesh; Islam, Aminul

doi:10.1049/iet-cds.2014.0167

Cited by 33 publications

(13 citation statements)

References 32 publications

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“…The process variability evaluation was taken, after the layout parasitic extraction The reference values from ASAP7 technology for electrical simulations are shown in Table 4.2. To avoid underestimating effects of realistic input waveforms on design metrics, the simulations were carried under a 5-bit ripple carry adder using copies of the 1-bit full adder cell with design metrics being calculated for the middle cell as shown in Source: Dokania and Islam (2015) 5 RESULTS AND DISCUSSION…”

Section: Electrical Simulationmentioning

confidence: 99%

“…Among these works there is [Dokania and Islam 2015] on which a novel technique based on the replacement of Full Adder's internal inverters with low voltage Schmitt Triggers for PVT variability robustness improvement is originally introduced and applied on seven different full adder designs. The simulations were performed using the 16nm bulk CMOS predictive technology model in SPICE.…”

Section: Variability Effects and Mitigation Techniquesmentioning

confidence: 99%

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Evaluation of variability using Schmitt trigger on full adders layout

Moraes

Zimpeck

Meinhardt

et al. 2018

Microelectronics Reliability

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The aggressive technology and voltage scaling which CMOS-based modern digital circuits are facing introduce challenges as short-channel effects, higher radiation and variability impact. As CMOS technology approaches its scaling limit, novel technology nodes, as FinFET, emerged to address such challenges. Although, even when shortchannel and radiation effects are mitigated due to technology instrinsic characteristics, the variability impact escalates with technology scaling and the lack of manufacturing precision. To mitigate that, novel techniques are proposed and tested in the literature. This work analyzes the impact on variability robustness using a technique based on the replacement of full adders internal inverters by Schmitt Triggers. Some works point that the given technique helps to improve the variability robustness at the electrical level. Therefore, analysis has been performed at layout level using the 7nm FinFET technology node from ASAP7 library and the technique was applied on four full adder designs. Performance, energy and area are taken into account. Results show up to 65% improvement on average delay and energy variability robustness, being necessary a trade-off analysis between robustness improvements and the impact on delays, power consumption and area.

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Section: Electrical Simulationmentioning

confidence: 99%

Section: Variability Effects and Mitigation Techniquesmentioning

confidence: 99%

Evaluation of variability using Schmitt trigger on full adders layout

Moraes

Zimpeck

Meinhardt

et al. 2018

Microelectronics Reliability

View full text Add to dashboard Cite

show abstract

“…The authors in [6] Designed Dynamic Gates that are aware of Noise existence. In [7] and [8] they discussed design techniques for process voltage variations. An Example of Bad Logic Problems in DSM Existing design unit of logic gates such as XOR has a noise induced glitch problem [9]- [10].…”

Section: Introductionmentioning

confidence: 99%

Novel Techniques for Noise-Tolerance in Combinational Critical-Path Circuit Components

Hafez*,

Mahmoud

2020

IJITEE

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The continued scaling of the device and interconnect in the deep submicron jurisdiction of the complementary metal oxide semiconductor (CMOS) very large scale design (VLSI) has brought many new design challenges and exposed the limitations of the traditional VLSI design. One of the most severe problems in the deep submicron is that the circuit tend to malfunction by producing incorrect outputs in the event of inputs that have glitch. Such noise problem has emerged as the critical reliability problem in the deep submicron, in addition to the power dissipation problem. In this proposal, new research is proposed to counter the noise problem through novel circuit design techniques and methodologies. As we continue in deep submicron, the reliability of such designs is reduced as the output levels of such circuit suffer because of voltage scaling. We present our research along with the results and then describe the further proposed research. The research techniques are described using the combinatorial gates which serve as the critical path component in many designs. Also, an efficient flip-flop CD, that is conditionally discharged when there is no input changes and the input remains high to high, is proposed. This new flip-flop reduces the switching state activity, and is almost glitch-less at the output. The results from our proposed techniques demonstrate at least 2.3x the noise-immunity over the best known results in the literature.

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“…In this proposal, new technique is proposed to counter the noise problem through novel circuit design techniques and methodologies. Despite the recent technique advances in designing noise-tolerant circuits, there is a vast gap between the noise-tolerance provided by such technique and the noise-tolerance that will be actually needed in the very deep submicron (VDSM) in order for the designs to function correctly [7]- [8]. For example, circuit components and design styles have been proposed that provide about 1.5 times to 2 times more noise immunity than the traditional VLSI design techniques.…”

Section: Introductionmentioning

confidence: 99%

Noise-Tolerant Circuits in Deep-Submicron using Delay Pass Transistor Circuit

Mahmoud*

2020

IJITEE

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In this paper, we propose a technique to increase the noise tolerance significantly over that of the existing circuit components and design styles. The paper proposes noise tolerance in the discrete, yet interrelated, areas of computational components design, powerless/groundless design style, dynamic circuit style, and memory design. Our results indicate a huge gain in noise-tolerance over the existing circuits and styles. The circuit components and design styles, developed by the technique, are integrated into architectures to study and demonstrate the combined effects of the techniques. This will be in addition to observing and analyzing the individual noise-tolerances of each components and circuit styles developed. We are proposing the limiter pass transistor technique, which is a new method to immune dynamic circuits from noise. Our proposed technique demonstrates 5.9X times gain in noise tolerance over the convectional dynamic circuit and 3.0 X gains over the best known method in the literature. Based on the preliminary proposed technique, we expect to come with dynamic circuit styles that can provide an order of magnitude more noiseimmunity.

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Circuit‐level design technique to mitigate impact of process, voltage and temperature variations in complementary metal‐oxide semiconductor full adder cells

Cited by 33 publications

References 32 publications

Evaluation of variability using Schmitt trigger on full adders layout

Evaluation of variability using Schmitt trigger on full adders layout

Novel Techniques for Noise-Tolerance in Combinational Critical-Path Circuit Components

Noise-Tolerant Circuits in Deep-Submicron using Delay Pass Transistor Circuit

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