Characterizing Quantum Devices at Scale with Custom Cryo-CMOS

Abstract

We make use of a custom-designed cryo-CMOS multiplexer (MUX) to enable multiple quantum devices to be characterized in a single cool-down of a dilution refrigerator. Combined with a packaging approach that integrates cryo-CMOS chips and a hot-swappable, parallel device test platform, we describe how this setup takes a standard wiring configuration as input and expands the capability for batch-characterization of quantum devices at milli-Kelvin temperatures and high magnetic fields. The architecture of the cryo-CMOS multiplexer is discussed and performance benchmarked using few-electron quantum dots and Hall mobility-mapping measurements.

Lambert-W function-based parameter extraction for FDSOI MOSFETs down to deep cryogenic temperatures

“…The MOSFET electrical parameters extraction is a key topic for CMOS technology characterization and optimization. With the advent of quantum computing, requiring CMOS readout electronics at cryogenic temperatures, there is a strong need for updating MOSFET parameter extraction methodologies in advanced technologies down to very low temperatures, 4.2K and below [1][2][3][4][5]. In the past years, such methodologies were developed in strong inversion region using conventional threshold voltage and mobility extraction procedures [6,7] or specific Y-function based extraction techniques [8,9].…”

Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

“…Although operational cryo-CMOS circuits have been demonstrated down to 30 mK [17,30,[68][69][70], unfortunately no mature models are yet available to accurately predict the behavior of passive and active devices at cryogenic temperatures [71,72]. Due to this lack of compact models at cryogenic temperatures, designers are faced to a blind-design procedure, which reduces the optimization of cryogenic integrated circuits [12,30,32,58,[73][74][75].…”

Microwaves in Quantum Computing

“…Consider, for instance, that as many as 10 wires are required within the 100 nm × 100 nm footprint of a spin qubit. This geometric I/O bottleneck motivates the integration of cryogenic electronics with the qubit platform to handle signal generation and multiplexing [146] without needing large cable assemblies that carry signals to room temperature electronics [147]. The power dissipation of these classical electronics can be significant, however, leading to heating of the qubits and a degradation in fidelity if tightly integrated in a monolithic configuration.…”