Characterization and reliability study of low temperature hermetic wafer level bonding using In/Sn interlayer and Cu/Ni/Au metallization

Progress in wafer bonding technology towards MEMS, high-power electronics, optoelectronics, and optofluidics

“…This phenomenon has been confirmed by the TEM observation, as shown in Figure 2(d). [9] To realize the commercial MEMS packaging using the In-Sn eutectic system, a buffer layer (e.g., Ti and Ni) is indispensable to prevent the solder consumption. In this way, high-quality waferlevel packaging has been realized by heating at 180 C for 20 min as shown in Figures 2(e) and (f).…”

“…[1][2][3][4][5][6] Many bonding methods have been developed for joining homo/ heterogeneous materials. [7][8][9] According to the intermediate layer is introduced or not during the bonding procedure, the bonding technology can be divided into two categories. The schematic illustration of categorization for wafer bonding technology is shown in Figure 1.…”

Bonding condition design methodology using Sn-Ag thin film for 3DIC

“…The bonding earliest first convex each other of thin film is in contact with an uneven, large pressure to the small area occurs. Local stress and contact area of the contact portion of the convex between the Sn is based on the Hertz theory, it can be determined as follows [7]. Radius r 0 of the contact surface of the case with a radius R 1 and R 2 of the sphere is pressurized by the force F is,…”

Low Temperature Wafer-Level Metal Thermo-Compression Bonding Technology for 3D Integration

“…Since the buffer layer is very thin, the Sn solder can diffuse into Cu in a short time. The research work by Yu et al (Yu et al, 2009) reports a 50nm Ni can be used as buffer layer during Cu/Sn/In eutectic bonding. A thin layer of Au has also been used for wetting and for metal layer surface protection from oxidation.…”