Case Study on Speed Failure Causes in a Microprocessor

Killpack, Kip; Natarajan, S.; Krishnamachary, Arun; Bastani, Pouria

doi:10.1109/mdt.2008.61

Cited by 31 publications

(18 citation statements)

References 5 publications

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“…CRITICAL STATE ELEMENT SELECTION Power droop which is the transient fluctuations in the power delivery network is an important cause of post-silicon timing errors [3]. Each logic cell or state element draws current from the power delivery network proportional to its size when it is switching.…”

Section: Trace Selection Algorithmmentioning

confidence: 99%

“…Recent case studies on industrial microprocessors have shown timing errors can be highly sensitive to internal signal transitions. Specifically those transitions which cause fluctuations in the power delivery network (i.e., power-droop) can significantly impact the path delays in nanometer technologies and thus cause timing errors [3]. Upon detecting a timing error, determining if the root-cause is power-droop is quite challenging because of the combination of the following factors: 1) the actual input patterns (e.g., instructions in a microprocessor) which result in excitation of an internal speedpath and subsequently in a timing error may not be known easily; 2) transient simulation of power delivery network is time-consuming; 3) low frequency droops may cause timing errors which are detected many cycles after the switching has occurred.…”

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confidence: 99%

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Trace signal selection to enhance timing and logic visibility in post-silicon validation

Shojaei¹,

Davoodi²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-Trace buffer technology allows tracking the values of a few number of state elements inside a chip within a desired time window,which is used to analyze logic errors during post-silicon validation. Due to limitation in the bandwidth of trace buffers, only few state elements can be selected for tracing. In this work we first propose two improvements to existing "signal selection" algorithms to further increase the logic restorability inside the chip. In addition, we observe that different selections of trace signals can result in the same quality, measured as a logic visibility metric. Based on this observation, we propose a procedure which biases the selection to increase the restorability of a desired set of critical state elements, without sacrificing the (overall) logic visibility. We propose to select the critical state elements to increase the "timing visibility" inside the chip to facilitate the debugging of timing errors which are perhaps the most challenging type of error to debug at the post-silicon stage. Specifically, we introduce a case when the critical state elements are selected to track the transient fluctuations in the power delivery network which can cause significant variations in the delays of the speedpaths in the circuit in nanometer technologies. This paper proposes to use the trace buffer technology to increase the timing visibility inside the chip, without sacrificing the logic visibility. I. INTRODUCTIONPost-silicon validation of VLSI chips has become significantly time-consuming in nanometer technologies and impacting the product time-to-market. Due to the high complexity of modern day electronic systems, logic bugs may escape the pre-silicon validation stage. However, at this stage, the lack of visibility to the signals inside the chip makes the validation a cumbersome task.Trace buffer technology has been recently used in order to track few internal state elements (i.e., signals) during the operation of a chip. These signals are selected for tracing at the design stage and the traces are analyzed at the post-silicon stage to debug logic errors. Many recent works have focused on the trace selection problem in order to maximize the chip logic visibility [4], [5], [6], where visibility is the metric used to reflect the degree of restoring the remaining state elements in the chip using the selected trace signals.In this work, we first present two enhancements to the existing trace selection algorithms:1. During computation of the visibility corresponding to a set of candidate trace signals, we show the ordering of state elements is very important. We discuss an ordering which results in more accurate computation of visibility during trace selection. 2. We propose a Pareto-algebriac procedure which in effect defers the selection of multiple trace signals, compared to existing greedy techniques which select one trace at each step. As a result, we can obtain a solution of higher visibility. Furthermore, we observe that due to the limited bandwidth of the trace buffer, many alternat...

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Section: Trace Selection Algorithmmentioning

confidence: 99%

mentioning

confidence: 99%

Trace signal selection to enhance timing and logic visibility in post-silicon validation

Shojaei¹,

Davoodi²

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…For a fabricated chip, the degree of variation might be such that the delays of some of the paths exceed their timing requirements. We assume such paths are isolated and their delays are measured as discussed in [1], [3], [5], [7], [9]. Moreover, we assume the delays of additional speedpaths are also measured.…”

Section: Preliminariesmentioning

confidence: 99%

“…To help identify such representative paths, in [3], a technique is proposed which relies on defining a set of basic features (e.g., the number or types of logic gates) to rank the target speedpaths. In [5], a manuallyguided technique is used to isolate failing speedpaths, via combination of techniques including clock shrinkage and using a debug tester. In [7], a branch-and-bound technique for isolation of speedpaths is proposed which is based on parameterized static timing analysis.…”

Section: Introductionmentioning

confidence: 99%

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Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Xie

Davoodi

Saluja

2010

Proceedings of the 47th Design Automation Conference

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We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay larger than their estimated delays at the pre-silicon stage. We refer to such segments as "failing segments" and we rank them according to their degree of failure. Diagnosis of failing segments alleviates the problem of lack of observability inside a path. Moreover, root-cause analysis, and post-silicon tuning or repair, can be done more effectively by focusing on the failing segments. We propose an Integer Linear Programming formulation to breakdown a path into a set of nonfailing segments, leaving the remaining to be likely-failing ones. Our algorithm yields a very high "diagnosis resolution" in identifying failing segments, and in ranking them.

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Automated Debugging for Logic Bugs

Dehbashi

Fey

2014

Debug Automation From Pre-Silicon to Post-Silicon

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Case Study on Speed Failure Causes in a Microprocessor

Cited by 31 publications

References 5 publications

Trace signal selection to enhance timing and logic visibility in post-silicon validation

Trace signal selection to enhance timing and logic visibility in post-silicon validation

Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Automated Debugging for Logic Bugs

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