Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations

Abstract

We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is applied after isolating the failing speedpaths which also incorporates post-silicon path-delay measurements for more accurate analysis. Our goal is to identify segments of the failing speedpaths that have a post-silicon delay larger than their estimated delays at the pre-silicon stage. We refer to such segments as "failing segments" and we rank them according to their degree of failure. Diagnosis of failing segments alleviates the problem of lack of observability inside a path. Moreover, root-cause analysis, and post-silicon tuning or repair, can be done more effectively by focusing on the failing segments. We propose an Integer Linear Programming formulation to breakdown a path into a set of nonfailing segments, leaving the remaining to be likely-failing ones. Our algorithm yields a very high "diagnosis resolution" in identifying failing segments, and in ranking them.

Debug Automation for Logic Circuits Under Timing Variations

“…SSTA methods analyze a circuit considering timing variations. The work in [3] proposes a formal procedure based on an integer linear programming (ILP) formulation to diagnose segments of failing speedpaths due to process variations. ILP is a specific case of a system of linear constraints in which the variables can only take integer values.…”

“…A speedpath is a frequency-limiting critical path which affects the performance of a chip [2]. A speedpath that violates timing constraints at the post-silicon stage is called failing speedpath [3]. Speedpaths fail due to, e.g., timing variations induced by process, design, and environmental effects [2].…”

E-beam lithography stencil planning and optimization with overlapped characters

“…Electronic Beam Lithography (EBL) is a maskless technique, which shoots desired patterns directly into a silicon wafer, and can potentially combat device parameter variations [13][14][15]. Various investigation [9][10][11][12] have been conducted on the optimization of character selection for EPL technology, where no intersection is allowed between templates on the stencil, as shown by Fig.…”

Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

“…Such methods measurably sensitize a path. Approaches in [6] [7] rely on specially fabricated paths which are assumed to be defect free, and [6] measured delays along them for post-silicon diagnosis of segment defects. However, such assumptions may not always hold.…”