Diagnosis of Performance Limiting Segments in Integrated Circuits Using Path Delay Measurements

Abstract

An approach capable of identifying the locations of distributed small delay defects, arising due to manufacturing aberrations, is proposed. It is shown that the proposed formulation can be transformed into a Boolean Satisfiability form to be solved by any SAT solver. The approach is capable of providing a small number of alternative sets of potential defective segments, and one of the solutions is the actual defect configuration. This is shown to be a very important property towards the effective identification of the defective segments. Experimental analysis on ISCAS and ITC benchmark suites show that the proposed approach is highly scalable and identifies the location of multiple delay defects.